Patents by Inventor Chih-Yi Huang
Chih-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11855034Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.Type: GrantFiled: May 28, 2021Date of Patent: December 26, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung-Hung Lai, Chin-Li Kao, Chih-Yi Huang, Teck-Chong Lee
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Publication number: 20230393194Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Tsung-Tang TSAI, Chih-Yi HUANG
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Patent number: 11733294Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: GrantFiled: March 6, 2020Date of Patent: August 22, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Tsung-Tang Tsai, Chih-Yi Huang
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Patent number: 11714215Abstract: An optical lens, mold for optical lens and manufacturing method thereof are provided, wherein the optical lens includes a spiral surface spiraling around an axial direction and an intermediate structure around which the spiral surface spirals, the intermediate structure extends axially relative to a side of the spiral surface, and two ends of the spiral surface defines a stepped difference. The structure of the mold and the optical lens are correspondingly complementary. The manufacturing method of the mold includes following steps of: providing a base, the base including a processing surface; processing the processing surface to form the spiral surface, the intermediate structure and the stepped difference of the mold.Type: GrantFiled: September 18, 2020Date of Patent: August 1, 2023Assignee: ORANGETEK CORPORATIONInventors: Chun-Chieh Chen, Chia-Jung Chang, Chih-Yi Huang, Chun-Yi Yeh
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Patent number: 11699654Abstract: An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.Type: GrantFiled: April 28, 2021Date of Patent: July 11, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shao-An Chen, Chih-Yi Huang, Ping Cing Shen
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Patent number: 11621220Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.Type: GrantFiled: March 25, 2021Date of Patent: April 4, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Shun Chang, Chih-Pin Hung, Teck-Chong Lee, Chih-Yi Huang
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Publication number: 20220399240Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: ApplicationFiled: August 22, 2022Publication date: December 15, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Chih-Yi HUANG, Keng-Tuan CHANG
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Publication number: 20220384381Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chung-Hung LAI, Chin-Li KAO, Chih-Yi HUANG, Teck-Chong LEE
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Patent number: 11515249Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.Type: GrantFiled: November 5, 2020Date of Patent: November 29, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Yi Huang, Chen-Chao Wang, Mi-Chun Hung
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Publication number: 20220352066Abstract: An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-An CHEN, Chih-Yi HUANG, Ping Cing SHEN
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Publication number: 20220310500Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Chih-Pin HUNG, Teck-Chong LEE, Chih-Yi HUANG
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Patent number: 11424167Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: GrantFiled: October 9, 2020Date of Patent: August 23, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Chih-Yi Huang, Keng-Tuan Chang
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Publication number: 20220139824Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Yi HUANG, Chen-Chao WANG, Mi-Chun HUNG
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Publication number: 20220115276Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: ApplicationFiled: October 9, 2020Publication date: April 14, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Chih-Yi HUANG, Keng-Tuan CHANG
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Publication number: 20220091305Abstract: An optical lens, mold for optical lens and manufacturing method thereof are provided, wherein the optical lens includes a spiral surface spiraling around an axial direction and an intermediate structure around which the spiral surface spirals, the intermediate structure extends axially relative to a side of the spiral surface, and two ends of the spiral surface defines a stepped difference. The structure of the mold and the optical lens are correspondingly complementary. The manufacturing method of the mold includes following steps of: providing a base, the base including a processing surface; processing the processing surface to form the spiral surface, the intermediate structure and the stepped difference of the mold.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Chun-Chieh Chen, Chia-Jung Chang, Chih-Yi Huang, Chun-Yi Yeh
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Publication number: 20210278457Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: ApplicationFiled: March 6, 2020Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Tsung-Tang TSAI, Chih-Yi HUANG
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Patent number: 10886263Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.Type: GrantFiled: September 29, 2017Date of Patent: January 5, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang
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Patent number: 10522508Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.Type: GrantFiled: May 1, 2018Date of Patent: December 31, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ian Hu, Ming-Han Wang, Tsun-Lung Hsieh, Chih-Yi Huang, Chih-Pin Hung
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Publication number: 20190341368Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ian HU, Ming-Han WANG, Tsun-Lung Hsieh, Chih-Yi HUANG, Chih-Pin HUNG
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Patent number: 10332849Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.Type: GrantFiled: September 4, 2018Date of Patent: June 25, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang-Lin Yeh, Jen-Chieh Kao, Chih-Yi Huang, Fu-Chen Chu