Patents by Inventor Chih-Yi Wang

Chih-Yi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015186
    Abstract: The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 9, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chun Lee, Chih-Yi Wang, Wei-Che Chen, Ya-Ting Hu, Yao-Jhan Wang, Kun-Szu Tseng, Feng-Yun Cheng, Shyan-Liang Chou
  • Publication number: 20240413017
    Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.
    Type: Application
    Filed: July 12, 2023
    Publication date: December 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Ya-Ting Hu, Wei-Che Chen, Chang-Yih Chen, Kun-Szu Tseng, Yao-Jhan Wang
  • Publication number: 20240379670
    Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.
    Type: Application
    Filed: June 6, 2023
    Publication date: November 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Ting Hu, Chih-Yi Wang, Yao-Jhan Wang, Wei-Che Chen, Kun-Szu Tseng, Yun-Yang He, Wen-Liang Huang, Lung-En Kuo, Po-Tsang Chen, Po-Chang Lin, Ying-Hsien Chen
  • Publication number: 20240363430
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 31, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Wei-Che Chen, Hung-Chun Lee, Yun-Yang He, Wei-Hao Chang, Chang-Yih Chen, Kun-Szu Tseng, Yao-Jhan Wang, Ying-Hsien Chen
  • Patent number: 12061413
    Abstract: An elevating mechanism includes a base member, a first movable member, a second movable member, a first magnetic member, and a second magnetic member, the first movable member is movably disposed on the base member, the second movable member is movably disposed on the base member, the first magnetic member disposed on the first movable member, the second magnetic member corresponds to the first magnetic member and is disposed on the second movable member, when the second movable member is in a holding position, the first magnetic member and the second magnetic member are attracted to each other.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: August 13, 2024
    Assignee: WISTRON CORP.
    Inventors: Kuang-Wen Chen, Chih-Yi Wang
  • Publication number: 20230333455
    Abstract: An elevating mechanism includes a base member, a first movable member, a second movable member, a first magnetic member, and a second magnetic member, the first movable member is movably disposed on the base member, the second movable member is movably disposed on the base member, the first magnetic member disposed on the first movable member, the second magnetic member corresponds to the first magnetic member and is disposed on the second movable member, when the second movable member is in a holding position, the first magnetic member and the second magnetic member are attracted to each other.
    Type: Application
    Filed: August 17, 2022
    Publication date: October 19, 2023
    Inventors: Kuang-Wen CHEN, CHIH-YI WANG
  • Patent number: 11569235
    Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: January 31, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
  • Publication number: 20210035977
    Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
  • Patent number: 10868011
    Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: December 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
  • Publication number: 20200203344
    Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
    Type: Application
    Filed: January 17, 2019
    Publication date: June 25, 2020
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
  • Publication number: 20200194589
    Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.
    Type: Application
    Filed: January 8, 2019
    Publication date: June 18, 2020
    Inventors: Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
  • Patent number: 10686079
    Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 16, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
  • Patent number: 10446682
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Publication number: 20190148550
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Patent number: 10283415
    Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
  • Publication number: 20190103492
    Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.
    Type: Application
    Filed: October 2, 2017
    Publication date: April 4, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Cheng-Pu Chiu, Pei-Yu Chen, Shih-Min Lu, Ming-Yueh Tsai, Yung-Sung Lin, Te-Chang Hsu, Chih-Yi Wang, Chi-Hsuan Cheng, Sheng-Chen Chung, Yao-Jhan Wang
  • Publication number: 20190080968
    Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.
    Type: Application
    Filed: September 10, 2017
    Publication date: March 14, 2019
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang
  • Patent number: 10217866
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Patent number: 10211107
    Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.
    Type: Grant
    Filed: September 10, 2017
    Date of Patent: February 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang
  • Publication number: 20190043760
    Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.
    Type: Application
    Filed: September 16, 2018
    Publication date: February 7, 2019
    Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng