Patents by Inventor Chih-Yi Wang

Chih-Yi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868011
    Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: December 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
  • Publication number: 20200203344
    Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.
    Type: Application
    Filed: January 17, 2019
    Publication date: June 25, 2020
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
  • Publication number: 20200194589
    Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.
    Type: Application
    Filed: January 8, 2019
    Publication date: June 18, 2020
    Inventors: Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
  • Patent number: 10686079
    Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 16, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
  • Patent number: 10446682
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Publication number: 20190148550
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Patent number: 10283415
    Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
  • Publication number: 20190103492
    Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.
    Type: Application
    Filed: October 2, 2017
    Publication date: April 4, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Cheng-Pu Chiu, Pei-Yu Chen, Shih-Min Lu, Ming-Yueh Tsai, Yung-Sung Lin, Te-Chang Hsu, Chih-Yi Wang, Chi-Hsuan Cheng, Sheng-Chen Chung, Yao-Jhan Wang
  • Publication number: 20190080968
    Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.
    Type: Application
    Filed: September 10, 2017
    Publication date: March 14, 2019
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang
  • Patent number: 10217866
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Patent number: 10211107
    Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.
    Type: Grant
    Filed: September 10, 2017
    Date of Patent: February 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang
  • Publication number: 20190043760
    Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.
    Type: Application
    Filed: September 16, 2018
    Publication date: February 7, 2019
    Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
  • Publication number: 20190027603
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.
    Type: Application
    Filed: September 6, 2017
    Publication date: January 24, 2019
    Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
  • Patent number: 10109531
    Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
  • Patent number: 9019721
    Abstract: A connection port module is mounted to a side wall of a housing of an electronic device. The electronic device includes a control circuit. The connection port module includes a rotating box, a circuit board, and at least one connection port. The rotating box is formed with at least one opening. The circuit board is electrically coupled to the control circuit. The connection port corresponds in number to the opening and is electrically coupled to the circuit board. The connection port is disposed correspondingly to the opening. The rotating box is pivotable relative to the housing between a first position and a second position.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: April 28, 2015
    Assignee: Wistron Corporation
    Inventors: Yu-Hsun Chen, Chih-Yi Wang, Cheng-Hung Lin
  • Patent number: 8824129
    Abstract: A frame assembly for installing panel modules with different dimensions is disclosed. The frame assembly includes a first frame and a second frame. The first frame has a first fixing structure formed thereon and a first sliding structure in an axis direction. The second frame has a second fixing structure formed thereon and a second sliding structure in the axis direction. The second sliding structure is slidably engaged with the first sliding structure. The first fixing structure and the second fixing structure are fixed on a side of a first panel module or on a side of a second panel module when the second frame slides relative to the first frame in the axis direction to a first position or to a second position.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: September 2, 2014
    Assignee: Wistron Corporation
    Inventors: Chih-Yi Wang, Ying-Chen Lin, Yu-Chi Chung
  • Patent number: 8705241
    Abstract: An electronic device includes a casing and a battery module removably locked to the casing. The casing includes a connecting wall, two inner side walls connected to opposite ends of the connecting wall and having pillars protruding therefrom, and a first magnetic member disposed at the connecting wall. The battery module includes a first side wall to abut against the connecting wall, and two second side walls connected to two opposite ends of the first sidewall. A second magnetic member is disposed at the first side wall and has a magnetic attraction force with the first magnetic member. Each second side wall is formed with a guiding groove extending along an insertion direction of the battery module for engaging a corresponding pillar.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 22, 2014
    Assignee: Wistron Corporation
    Inventors: Cheng-Hung Lin, Chih-Yi Wang, Wen-Tai Lin
  • Patent number: 8660291
    Abstract: A speaker device is disclosed. The speaker device is mounted in an electronic device that includes a plurality of positioning elements. The speaker device includes a speaker main body, at least one pair of buffer arms, a plurality of fixed elements, and a plurality of buffer members. One end of each buffer arms is connected to the speaker main body and located at the opposite sides of the speaker main body. The fixed elements is connected to the other end of each buffer arm and movably combined with each positioning element, such that the speaker main body is fixed in the electronic device. The members is mounted in between each fixed element and each positioning element, allowing the buffer arms and the buffer members to reduce vibration generated by the speaker main body passing to the electronic device when the speaker main body is vibrating.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Wistron Corporation
    Inventor: Chih-Yi Wang
  • Patent number: 8659551
    Abstract: An electronic apparatus including a shell, a door plate, a support member, and a pointing input device is disclosed. The shell comprises an aperture; the door plate is connected to the shell, and can be moved to cover the aperture; the support member is positioned inside the shell, and includes a first position and a second position, wherein the distance between the first position and the aperture is larger than the distance between the second position and the aperture; when the aperture is covered by the door plate, the pointing input device is mounted in the first position, and can be moved to the second position when the aperture is not covered by the door plate, such that the pointing input device can extend from the shell.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: February 25, 2014
    Assignee: Wistron Corporation
    Inventors: Tsung-Ying Tsai, Chih-Yi Wang
  • Patent number: 8582797
    Abstract: A portable electronic device includes a housing. An opening is formed on the housing and a containing space is formed inside the housing. The portable electronic device further includes a speaker installed inside the containing space in a rotatable manner, a first magnetic component installed on a side of the speaker, a second magnetic component installed inside the housing and disposed on a side of the containing space for attracting the first magnetic component so as to position the first magnetic component on a first location, and a restoring component connected to the speaker for driving the speaker to rotate to a second location so as to expose the speaker outside the opening on the housing when magnetic attractive force between the first magnetic component and the second magnetic component disappears.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: November 12, 2013
    Assignee: Wistron Corporation
    Inventor: Chih-Yi Wang