Patents by Inventor Chih-Yu Lin
Chih-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150214063Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.Type: ApplicationFiled: January 29, 2014Publication date: July 30, 2015Inventors: Hans-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Patent number: 9087793Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.Type: GrantFiled: December 11, 2013Date of Patent: July 21, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen Liao, Wei-Tai Lin, Wen-Sheng Wang, Chih-Yu Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
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Publication number: 20150179531Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Patent number: 9064741Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.Type: GrantFiled: December 20, 2013Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
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Publication number: 20150162206Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen LIAO, Wei-Tai LIN, Wen-Sheng WANG, Chih-Yu LIN, Cherng-Chang TSUEI, Chen-Hsiang LU
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Publication number: 20150130068Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.Type: ApplicationFiled: November 12, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yu LIN, Kao-Cheng LIN, Li-Wen WANG, Yen-Huei CHEN
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Publication number: 20140350874Abstract: The present invention is to provide a sensing method applicable to a sensing system including at least one detecting device and a mobile communication device, wherein the detecting device is electrically connected between an electrical appliance and a power supply unit for detecting usage information (e.g., voltage value, current value, power value, etc.) of the electricity transmitted from the power supply unit to the electrical appliance, and the mobile communication device is wirelessly connected to the detecting device and is able to transmit setting data inputted by a user to the detecting device so that, after receiving the setting data, the detecting device is able to periodically transmit the electricity usage information to the mobile communication device, allowing the mobile communication device to convert the electricity usage information into a detecting chart and graphically display the detecting chart on a screen of the mobile communication device.Type: ApplicationFiled: July 25, 2013Publication date: November 27, 2014Applicant: D-Link CorporationInventors: Chih-Yu LIN, Jia-Liang LIAO, Jia-Ming LIANG, Yu-Chee TSENG, Cheng-Yi YAN
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Publication number: 20140269024Abstract: A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at the first voltage level for a first predetermined duration. The voltage level at the power terminal of the memory cell is maintained at a second voltage level for a second predetermined duration, where the second voltage level is between the first voltage level and the supply voltage level. During the write cycle, the voltage level at the power terminal of the memory cell is caused to change from the first voltage level toward the supply voltage level.Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Huei CHEN, Li-Wen WANG, Chih-Yu LIN
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Publication number: 20140211578Abstract: One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Huei Chen, Chih-Yu Lin, Li-Wen Wang, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Patent number: 8773923Abstract: A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided.Type: GrantFiled: July 30, 2012Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Huei Chen, Li-Wen Wang, Chih-Yu Lin
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Publication number: 20140143240Abstract: An information search server and an information search method thereof are provided. The information search server includes a transceiver and a processor. The transceiver receives a search message having an original store phone number of an original store from a user device. The processor performs a data mining procedure, according to the original store phone number, to obtain an original store name and an original store address associated with the original store phone number, a category associated with the original store name, an original store latitude and longitude associated with the original store address, and a recommended store information associated with the category and the original store latitude and longitude, and generates a result message having the recommended store information. The transceiver further transmits the result message to the user device.Type: ApplicationFiled: February 17, 2013Publication date: May 22, 2014Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Yu-Chee TSENG, Chih-Yu LIN, Jia-Ming LIANG, You-Ren CHU, Chien-Yi LI, Hsin-Yu CHANG, Chih-Yang CHUANG, Chih-Chiang HSIEH
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Publication number: 20140119101Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Li-Wen Wang, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
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Publication number: 20140029358Abstract: A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Huei CHEN, Li-Wen WANG, Chih-Yu LIN
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Patent number: 8559251Abstract: A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.Type: GrantFiled: January 20, 2012Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yu Lin, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Publication number: 20130188433Abstract: A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yu LIN, Wei Min CHAN, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG
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Patent number: 8379589Abstract: A node apparatus and an adjusting method of a quantity of nodes for a sensor network and a tangible machine-readable medium thereof are provided. The sensor network comprises a plurality of groups, wherein each group has a plurality of nodes. For each group, one of the nodes is set to be a gate node, and each node within the group transmits at least one data of itself to the corresponded gate node. Each gate node calculates a data aggregation time based on a data length per unit time of received data and a predetermined packet length, so that each gate node is able to adjust the quantity of nodes within the group thereof accordingly.Type: GrantFiled: June 3, 2009Date of Patent: February 19, 2013Assignee: Institute for Information IndustryInventors: Chih-Yu Lin, Yung-Chih Liu, Che-Hsi Chuang, Yu-Chee Tseng
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Patent number: 8295627Abstract: The present invention provides a circuit for controlling a color sequential liquid crystal display (LCD) and a method for controlling the same. The control circuit comprises a light-source driving circuit, a data driving circuit, and a scan driving circuit. The light-source driving circuit produces a driving signal for controlling the color sequential LCD to produce backlight with different colors. The data driving circuit produces a data signal and includes a plurality of data pulses. The scan driving signal produces a scan signal and includes a plurality of scan pulses corresponding to the plurality of data pulses, respectively. By controlling the pluralities of data pulses and scan pulses and the backlight, the color sequential LCD will display an image. The voltage levels of the pluralities of data pulses and scan pulses change according to different images. Thereby, power consumed by the control circuit can be reduced. In addition, color-mixing problems will be reduced according to the present invention.Type: GrantFiled: October 20, 2008Date of Patent: October 23, 2012Assignee: Sitronix Technology Corp.Inventors: Chih-Yu Lin, Chao-Chu Chang
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Patent number: 8290290Abstract: A control IC (integrated circuit) for color sequential liquid crystal displays (LCD) is revealed. The control IC includes an interface for receiving a command and at least one display data and a timing generator to generate a scan timing signal, a data timing signal, and a driving timing signal. According to the scan timing signal, a scan driving circuit generates a scan signal that is sent to the color sequential LCD. In accordance with the data timing signal, a data driving circuit receives the display data for generating a data signal sent to the color sequential LCD. According to the driving timing signal, a light-source driving circuit generates a plurality of driving signals sent to the color sequential LCD so as to generate a plurality of color backlights. In accordance with the scan signal, the data signal and the plurality of backlights, the color sequential LCD displays a frame.Type: GrantFiled: October 20, 2008Date of Patent: October 16, 2012Assignee: Sitronix Technology Corp.Inventors: Chin-Wei Chien, Ting-Long Kuo, Kai-Yi Wu, Chung-Yao Hu, Hong-Zhung Zhu, Chih-Yu Lin, Chao-Chu Chang, Chia-Jung Lin, Lung-Hui Wang
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Patent number: 8148756Abstract: A separative extended gate field effect transistor based uric acid sensing device is provided, including: a substrate; a conductive layer including a silver paste layer on the substrate and a graphite-based paste layer on the silver paste layer; a conductive wire extended from the conductive layer; a titanium dioxide layer on the conductive layer; and a uric acid enzyme sensing film on the titanium dioxide layer.Type: GrantFiled: March 25, 2009Date of Patent: April 3, 2012Assignee: National Yunlin University of Science and TechnologyInventors: Jung-Chuan Chou, Chih-Yu Lin, Wei-Chuan Chen, Cheng-Wei Chen
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Publication number: 20100220072Abstract: A modulized touch panel is revealed. The modulized touch panel includes a first substrate layer and a second substrate layer while the second substrate layer is corresponding to the first substrate layer A touch panel is integrated with a control chip so as to reduce complexity and occupied area of the circuit that transmits signals between electronic devices and the touch panel while increasing scan lines of the touch panel. Thus circuit of electronics is simplified. Moreover, the first substrate layer or the second substrate layer of the touch panel is disposed with a metal layer for reducing impedance and improving signal stability.Type: ApplicationFiled: January 22, 2010Publication date: September 2, 2010Applicant: SITRONIX TECHNOLOGY CORP.Inventors: CHIN-WEI CHIEN, CHIH-YU LIN, HAN-CHAO CHEN