Patents by Inventor Chih-Yu Tseng

Chih-Yu Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11430909
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Publication number: 20210351215
    Abstract: Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Inventors: Chih-Yu TSENG, Ming-Hsien CHEN
  • Patent number: 10157981
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first conductive type well region in the substrate, and a second conductive type well region in the substrate. The first conductive type is different from the second conductive type. The first conductive type well region partially overlaps the second conductive type well region in an overlapping region. The semiconductor device structure also includes a source portion in the first conductive type well region and a drain portion in the second conductive type well region. The semiconductor device structure further includes a gate structure over the substrate and the overlapping region, and between the source portion and the drain portion. The semiconductor device structure further includes a first conductive type doping region in the first conductive type well region and the overlapping region.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu Tseng, Chia-Pin Hung, Ming-Hsien Chen
  • Patent number: 9041155
    Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 26, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
  • Patent number: 8912844
    Abstract: The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-Lin Li, Chun-Chang Wu, Chih-Yu Tseng
  • Patent number: 8716802
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: May 6, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Publication number: 20140097890
    Abstract: The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzung-Lin Li, Chun-Chang Wu, Chih-Yu Tseng
  • Patent number: 8664705
    Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
  • Patent number: 8637936
    Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 28, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
  • Publication number: 20140008762
    Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
  • Publication number: 20130320421
    Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
  • Patent number: 8558346
    Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: October 15, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
  • Patent number: 8507987
    Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 13, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
  • Patent number: 8477475
    Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 2, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
  • Patent number: 8357988
    Abstract: A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: January 22, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Chou Hung, Victor-Chiang Liang, Jui-Meng Jao, Cheng-Hung Li, Sheng-Yi Huang, Tzung-Lin Li, Huai-Wen Zhang, Chih-Yu Tseng
  • Patent number: 8350337
    Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • Patent number: 8349682
    Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Patent number: 8252657
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Grant
    Filed: March 27, 2011
    Date of Patent: August 28, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • Publication number: 20120214284
    Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 23, 2012
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Patent number: 8193900
    Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: June 5, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang