Patents by Inventor Chih-Yu Tseng

Chih-Yu Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8507987
    Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 13, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
  • Patent number: 8477475
    Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 2, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
  • Patent number: 8357988
    Abstract: A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: January 22, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Chou Hung, Victor-Chiang Liang, Jui-Meng Jao, Cheng-Hung Li, Sheng-Yi Huang, Tzung-Lin Li, Huai-Wen Zhang, Chih-Yu Tseng
  • Patent number: 8350337
    Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • Patent number: 8349682
    Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Patent number: 8252657
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Grant
    Filed: March 27, 2011
    Date of Patent: August 28, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • Publication number: 20120214284
    Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 23, 2012
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Patent number: 8193900
    Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: June 5, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Patent number: 8093118
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 10, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Szu Tseng, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • Publication number: 20110292565
    Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.
    Type: Application
    Filed: August 4, 2011
    Publication date: December 1, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
  • Patent number: 8027144
    Abstract: A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: September 27, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
  • Patent number: 7994576
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 9, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • Publication number: 20110171810
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Application
    Filed: March 27, 2011
    Publication date: July 14, 2011
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • Publication number: 20110156161
    Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • Publication number: 20110073957
    Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 31, 2011
    Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
  • Publication number: 20110068415
    Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 24, 2011
    Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
  • Publication number: 20100327378
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Applicant: United Microelectronics Corp.
    Inventors: KUN-SZU TSENG, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • Publication number: 20100328022
    Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Publication number: 20100320540
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Application
    Filed: August 9, 2010
    Publication date: December 23, 2010
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Publication number: 20100320544
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 23, 2010
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang