Patents by Inventor Chih-Yu Tseng
Chih-Yu Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8507987Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.Type: GrantFiled: September 21, 2009Date of Patent: August 13, 2013Assignee: United Microelectronics Corp.Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
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Patent number: 8477475Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.Type: GrantFiled: August 4, 2011Date of Patent: July 2, 2013Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Patent number: 8357988Abstract: A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.Type: GrantFiled: February 6, 2009Date of Patent: January 22, 2013Assignee: United Microelectronics Corp.Inventors: Cheng-Chou Hung, Victor-Chiang Liang, Jui-Meng Jao, Cheng-Hung Li, Sheng-Yi Huang, Tzung-Lin Li, Huai-Wen Zhang, Chih-Yu Tseng
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Patent number: 8350337Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.Type: GrantFiled: December 29, 2009Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Patent number: 8349682Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: GrantFiled: May 2, 2012Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Patent number: 8252657Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: GrantFiled: March 27, 2011Date of Patent: August 28, 2012Assignee: United Microelectronics Corp.Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
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Publication number: 20120214284Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: ApplicationFiled: May 2, 2012Publication date: August 23, 2012Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Patent number: 8193900Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: GrantFiled: June 24, 2009Date of Patent: June 5, 2012Assignee: United Microelectronics Corp.Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Patent number: 8093118Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.Type: GrantFiled: June 26, 2009Date of Patent: January 10, 2012Assignee: United Microelectronics Corp.Inventors: Kun-Szu Tseng, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Publication number: 20110292565Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.Type: ApplicationFiled: August 4, 2011Publication date: December 1, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Patent number: 8027144Abstract: A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes.Type: GrantFiled: April 28, 2009Date of Patent: September 27, 2011Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Patent number: 7994576Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: GrantFiled: June 22, 2009Date of Patent: August 9, 2011Assignee: United Microelectronics Corp.Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
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Publication number: 20110171810Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: ApplicationFiled: March 27, 2011Publication date: July 14, 2011Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
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Publication number: 20110156161Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Publication number: 20110073957Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
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Publication number: 20110068415Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
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Publication number: 20100327378Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Applicant: United Microelectronics Corp.Inventors: KUN-SZU TSENG, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
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Publication number: 20100328022Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.Type: ApplicationFiled: June 24, 2009Publication date: December 30, 2010Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
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Publication number: 20100320540Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: ApplicationFiled: August 9, 2010Publication date: December 23, 2010Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Publication number: 20100320544Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.Type: ApplicationFiled: June 22, 2009Publication date: December 23, 2010Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang