Patents by Inventor Chih-Yu Wu

Chih-Yu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250070297
    Abstract: An energy storage cabinet includes a frame supporting multiple battery packs and a cooling device. The frame includes a support with a pipe and a partition dividing an internal fluid passage of the pipe into a first flow channel and a second flow channel. Each battery pack has a first vent and a second vent. The second vent of a first battery pack is in communication with the second flow channel. The first vent of a second battery pack is in communication with the first flow channel. The cooling device produces a cool air entering the first vent of the first battery pack and the first flow channel. As the cool air passes through the first battery pack, the cool air is heated and becomes a warm air, which is then discharged into the second flow channel through the second vent.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Inventors: Chin-Ming CHEN, Chih-Yu WU, Yen-Kai PENG
  • Publication number: 20250070314
    Abstract: A battery pack includes a housing, a plurality of battery cells and a liquid filling device. The battery cells are disposed in the housing, and each of the battery cells includes two electrodes. The housing has a side opening. A lower edge of the side opening is positioned below the electrodes in a vertical direction. The liquid filling device is connected to the housing and is configured to fill a cooling liquid into the housing. The side opening of the housing is configured to allow excessive cooling liquid to be discharged out of the housing.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Inventors: Chin-Ming CHEN, Chih-Yu WU, Yen-Kai PENG
  • Publication number: 20250070398
    Abstract: A battery cell interconnection component includes a multi-layer structure and two holders. The multi-layer structure includes a plurality of metal strips in a stack arrangement. A gap is formed between any two immediately adjacent metal strips. The two holders fixedly clamp two ends of the multi-layer structure, and each of the two holders is configured to be electrically connected to an electrode of a battery cell.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Inventors: Chin-Ming CHEN, Chih-Yu WU, Yen-Kai PENG
  • Patent number: 11214868
    Abstract: The present disclosure provides a blocker plate, including a plate body having a plurality of through holes, a first zone from a center to a first radius of the plate body, having a first conductance, a second zone from the first radius to a second radius of the plate body, having a second conductance, a third zone from the second radius to a third radius of the plate body, having a third conductance, wherein the first radius is smaller than the second radius, the second radius is smaller than the third radius, and the second conductance is greater than the first conductance. A chemical vapor deposition (CVD) apparatus including the blocker plate is also disclosed.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Chieh Chen, Chao-Chun Wang, Chih-Yu Wu, Keith Kuang-Kuo Koai
  • Publication number: 20200194301
    Abstract: A metal interconnection includes a substrate, a first dielectric layer, metal wirings, air gaps and air gap dummies. The substrate includes an isolated area and a dense area. The first dielectric layer is disposed over the substrate. The metal wirings are embedded in the first dielectric layer, wherein the density of the metal wirings in the isolated area is less than the density of the metal wirings in the dense area. The air gaps are sandwiched by the metal wirings. The air gap dummies are disposed in the first dielectric layer without contacting the metal wirings. The present invention also provides a method of forming a metal interconnection.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Chih-Yu Wu, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Guan-Kai Huang
  • Publication number: 20200131640
    Abstract: The present disclosure provides a blocker plate, including a plate body having a plurality of through holes, a first zone from a center to a first radius of the plate body, having a first conductance, a second zone from the first radius to a second radius of the plate body, having a second conductance, a third zone from the second radius to a third radius of the plate body, having a third conductance, wherein the first radius is smaller than the second radius, the second radius is smaller than the third radius, and the second conductance is greater than the first conductance. A chemical vapor deposition (CVD) apparatus including the blocker plate is also disclosed.
    Type: Application
    Filed: June 27, 2019
    Publication date: April 30, 2020
    Inventors: HUAN-CHIEH CHEN, CHAO-CHUN WANG, CHIH-YU WU, KEITH KUANG-KUO KOAI
  • Die
    Patent number: 10510677
    Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yung-Teng Tsai, Hung-Chin Lin, Chia-Chen Sun, Chih-Yu Wu, Jun-Ming Chen, Chung-Chih Hung, Sheng-Chieh Chen
  • Patent number: 10336692
    Abstract: The present invention provides a method of forming paracyclyophane containing disulfide functional group. The paracyclophane is prepared by adding 3,3?-dithiodipropionic acid (DPDPA) and N-ethyl-N?-(3-(dimethylamino)propyl)carbodiimide (EDC) into 4-aminomethyl [2,2] paracyclophane. The present invention further provides a chemical film and a method of forming the same. The chemical film contains poly-p-xylylene with disulfide functional group and is formed on a substrate by a chemical vapor deposition process.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: July 2, 2019
    Assignee: MAY-HWA ENTERPRISE CORPORATION
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan, Chih-Yu Wu
  • Patent number: 10246412
    Abstract: The present invention provides a method of forming paracyclyophane containing disulfide functional group. The paracyclophane is prepared by adding 3,3?-dithiodipropionic acid (DPDPA) and N-ethyl-N?-(3-(dimethylamino)propyl)carbodiimide (EDC) into 4-aminomethyl [2,2] paracyclophane. The present invention further provides a chemical film and a method of forming the same. The chemical film contains poly-p-xylylene with disulfide functional group and is formed on a substrate by a chemical vapor deposition process.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 2, 2019
    Assignee: MAY-HWA ENTERPRISE CORPORATION
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan, Chih-Yu Wu
  • Patent number: 10156526
    Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yung-Teng Tsai, Hung-Chin Lin, Chia-Chen Sun, Chih-Yu Wu, Jun-Ming Chen, Chung-Chih Hung, Sheng-Chieh Chen
  • DIE
    Publication number: 20180356348
    Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Yung-Teng Tsai, Hung-Chin Lin, Chia-Chen Sun, Chih-Yu Wu, Jun-Ming Chen, Chung-Chih Hung, Sheng-Chieh Chen
  • Publication number: 20180356347
    Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Yung-Teng Tsai, Hung-Chin Lin, Chia-Chen Sun, Chih-Yu Wu, Jun-Ming Chen, Chung-Chih Hung, Sheng-Chieh Chen
  • Patent number: 10141362
    Abstract: A semiconductor device having a protection layer wrapping around a conductive structure is provided. The semiconductor device comprises an image sensor device layer, an interconnect layer over the image sensor device layer, a first bonding layer over the interconnect layer, a second bonding layer bonded with the first bonding layer, a substrate over the second bonding layer, and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer. The conductive via comprises a protection layer and a conductive material. The protection layer is peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer. The protection layer covers a sidewall cut formed at an interface of the second bonding layer and the first bonding layer. The conductive material is peripherally enclosed by the protection layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Sung, Yi-Hung Chen, Keng-Ying Liao, Yi-Fang Yang, Chih-Yu Wu
  • Publication number: 20180315790
    Abstract: A semiconductor device having a protection layer wrapping around a conductive structure is provided. The semiconductor device comprises an image sensor device layer, an interconnect layer over the image sensor device layer, a first bonding layer over the interconnect layer, a second bonding layer bonded with the first bonding layer, a substrate over the second bonding layer, and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer. The conductive via comprises a protection layer and a conductive material. The protection layer is peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer. The protection layer covers a sidewall cut formed at an interface of the second bonding layer and the first bonding layer. The conductive material is peripherally enclosed by the protection layer.
    Type: Application
    Filed: March 12, 2018
    Publication date: November 1, 2018
    Inventors: Chih-Wei Sung, Yi-Hung Chen, Keng-Ying Liao, Yi-Fang Yang, Chih-Yu Wu
  • Patent number: 10082471
    Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: September 25, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yung-Teng Tsai, Hung-Chin Lin, Chia-Chen Sun, Chih-Yu Wu, Jun-Ming Chen, Chung-Chih Hung, Sheng-Chieh Chen
  • Publication number: 20180265460
    Abstract: The present invention provides a method of forming paracyclyophane containing disulfide functional group. The paracyclophane is prepared by adding 3,3?-dithiodipropionic acid (DPDPA) and N-ethyl-N?-(3-(dimethylamino)propyl)carbodiimide (EDC) into 4-aminomethyl [2,2] paracyclophane. The present invention further provides a chemical film and a method of forming the same. The chemical film contains poly-p-xylylene with disulfide functional group and is formed on a substrate by a chemical vapor deposition process.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 20, 2018
    Inventors: Hsien-Yeh Chen, Zhen-Yu Guan, Chih-Yu Wu
  • Patent number: 10035875
    Abstract: A patterned film structure consists of a substrate and of a patterned polymeric layer which selectively covers and exposes part of the surface of the substrate. The patterned polymeric layer is selected form at least one of an unsubstituted poly-para-xylylene and a substituted poly-para-xylylene.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 31, 2018
    Assignee: MAY-HWA ENTERPRISE CORPORATION
    Inventors: Hsien-Yeh Chen, Chih-Yu Wu
  • Publication number: 20180188185
    Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
    Type: Application
    Filed: January 2, 2017
    Publication date: July 5, 2018
    Inventors: Yung-Teng Tsai, Hung-Chin Lin, Chia-Chen Sun, Chih-Yu Wu, Jun-Ming Chen, Chung-Chih Hung, Sheng-Chieh Chen
  • Patent number: 9929203
    Abstract: A semiconductor device and a method for fabricating thereof are provided. In the method for fabricating the semiconductor device, at first, a first semiconductor wafer including a first oxide layer and a second semiconductor wafer including a second oxide layer are provided. Next, the second oxide layer is bonded with the first oxide layer. Then, a through via is formed to through the second oxide layer and the first oxide layer, so as to form a sidewall cut on a sidewall of the through via at an interface of the first oxide layer and the second oxide layer. Then, an ashing operation is performed on the sidewall of the through via to form a protection layer on the sidewall of the through via. After the ashing operation is performed, a conductive material is deposited on the through via.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: March 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Sung, Yi-Hung Chen, Keng-Ying Liao, Yi-Fang Yang, Chih-Yu Wu
  • Publication number: 20170349697
    Abstract: A patterned film structure consists of a substrate and of a patterned polymeric layer which selectively covers and exposes part of the surface of the substrate. The patterned polymeric layer is selected form at least one of an unsubstituted poly-para-xylylene and a substituted poly-para-xylylene.
    Type: Application
    Filed: March 7, 2017
    Publication date: December 7, 2017
    Inventors: Hsien-Yeh Chen, Chih-Yu Wu