Patents by Inventor Chih-Yuan Cheng

Chih-Yuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7754599
    Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: July 13, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Rong-Chang Feng, Ra-Min Tain, Shyi-Ching Liau, Ji-Cheng Lin, Shan-Pu Yu, Shou-Lung Chen, Chih-Yuan Cheng
  • Publication number: 20100067295
    Abstract: A refresh method for a non-volatile memory for preventing disturb phenomenon includes reading data of a memory unit of the non-volatile memory at a first time point within a predefined period and storing the data in a buffer, determining whether data of the memory unit and data of the buffer are identical at a second time point within the predefined period, so as to generate a determination result, and refreshing the memory unit according to the determination result.
    Type: Application
    Filed: December 7, 2008
    Publication date: March 18, 2010
    Inventors: Ching-Fang Yen, Che-Heng Lai, Chih-Yuan Cheng
  • Publication number: 20100061153
    Abstract: A refresh method for a non-volatile memory for preventing disturb phenomenon includes dividing a plurality of sectors of a block of the non-volatile memory into a plurality of groups, determining a first group of the plurality of groups according to a first value when a first sector of the plurality of sectors is performed an erase operation, and reading and rewriting data of sectors of the first group.
    Type: Application
    Filed: December 26, 2008
    Publication date: March 11, 2010
    Inventors: Ching-Fang Yen, Che-Heng Lai, Chih-Yuan Cheng
  • Publication number: 20090294947
    Abstract: A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.
    Type: Application
    Filed: May 13, 2009
    Publication date: December 3, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ra-Min Tain, Yu-Lin Chao, Shu-Jung Yang, Rong-Chang Fang, Wei Li, Chih-Yuan Cheng, Ming-Che Hsieh
  • Publication number: 20090245308
    Abstract: An active solid heatsink device and fabricating method thereof is related to a high-effective solid cooling device, where heat generated by a heat source with a small area and a high heat-generating density diffuses to a whole substrate using a heat conduction characteristic of hot electrons of a thermionic (TI) structure, and the thermionic (TI) structure and a thermo-electric (TE) structure share the substrate where the heat diffuses to. Further, the shared substrate serves as a cold end of the TE structure, and the heat diffusing to the shared substrate is pumped to another substrate of the TE structure serving as a hot end of the TE structure.
    Type: Application
    Filed: December 16, 2008
    Publication date: October 1, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Kuang YU, Chun-Kai LIU, Ming-Ji DAI, Chih-Yuan CHENG
  • Publication number: 20090156001
    Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
    Type: Application
    Filed: February 17, 2009
    Publication date: June 18, 2009
    Inventors: Yung-Yu Hsu, Rong-Chang Feng, Ra-Min Tain, Shyi-Ching Liau, Ji-cheng Lin, Shan-Pu Yu, Shou-Lung Chen, Chih-Yuan Cheng
  • Publication number: 20080074914
    Abstract: A memory device comprises a first memory cell and a second memory cell. The first memory cell includes a first transistor coupled to a bit line and the second memory cell includes a second transistor coupled to a bit line bar. The first transistor includes a first gate terminal coupled to a first word line. The second transistor includes a second gate terminal coupled to a second word line. The first transistor and the second transistor are controlled by the first word line and the second word line respectively. A first sense amplifier having an asymmetric configuration is coupled to the bit line and the bit line bar and is capable to sense a status of at least one of the bit line and the bit line bar.
    Type: Application
    Filed: September 21, 2007
    Publication date: March 27, 2008
    Applicant: MEMOCOM CORP.
    Inventors: Hong-Gee FANG, Wen-Chieh LEE, Ching-Wen CHEN, Chih-Yuan CHENG, Chung-Cheng WU
  • Publication number: 20060102320
    Abstract: A heat sink is disclosed. A plurality of fins is radially and uniformly connected to a central base. Each fin comprises a plurality of protrusions. The protrusions are uniformly formed on each fin around the circumference of the central base.
    Type: Application
    Filed: October 4, 2005
    Publication date: May 18, 2006
    Inventors: Chi-Chang Lin, Chih-Yuan Cheng, Heng-Tsung Wang
  • Publication number: 20050288064
    Abstract: A function key control system integrating a function reminder menu, an assistant description menu and a function set-up menu and a controlling method thereof are provided. The controlling method comprises steps of using an embedded controller in an electronic equipment to detect that a first key is activated. The embedded controller transmits a trigger signal to fire up an application program. The application program opens and displays a function reminder menu. The embedded controller detects that a second key is activated and diagnoses a type of the second key. According to the type of the second key, either a function corresponding to the second key is performed or an assistant description menu and a function set-up menu are opened or the application program is terminated.
    Type: Application
    Filed: October 19, 2004
    Publication date: December 29, 2005
    Inventors: Cheng-Shuo Lin, Chih-Yuan Cheng
  • Publication number: 20050040895
    Abstract: A low power consumption oscillation circuit and a delay circuit thereof are disclosed. The circuit comprises an enable circuit, an oscillator delay circuit and a feedback control network. The enable circuit is adapted for receiving an enable signal and performing an initial oscillation. The enable circuit outputs an initial oscillation signal according to a feedback control signal. The oscillator delay circuit is coupled to the enable circuit and is adapted for alternately generating a high and a low level oscillation signals according to the initial oscillation signal. The feedback control network is coupled to the oscillator delay circuit and is adapted for integrating the high and the low level oscillation signals to generate a feedback control signal and outputting the feedback control signal to the enable the circuit for activating next oscillation.
    Type: Application
    Filed: August 2, 2004
    Publication date: February 24, 2005
    Inventors: Hong-Gee Fang, Wen-Chieh Lee, Chih-Yuan Cheng
  • Patent number: 6505151
    Abstract: The process of dividing sentences into phrases is automated. The sentence is divided into sub-sentences using statistical analysis. Then, the sub-sentences are into phrases, using statistical analysis. For example, for each pair of adjacent words in the sentence a metric is calculated which represents a strength of disconnection between the adjacent words. The sentence is divided into sub-sentences at locations in the sentence where the metric exceeds a first threshold.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: January 7, 2003
    Assignee: Bridgewell Inc.
    Inventors: Peilin Chou, Yen-Jen Oyang, Kuang-Hua Chen, Tien-Hsiung Sung, Chih-Yuan Cheng
  • Patent number: D509194
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: September 6, 2005
    Assignee: ASUSTek Computer Inc.
    Inventors: Chi-Chang Lin, Chih-Yuan Cheng, Heng-Tsung Wang
  • Patent number: D510324
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 4, 2005
    Assignee: ASUSTek Computer Inc.
    Inventors: Chi-Chang Lin, Chih-Yuan Cheng, Heng-Tsung Wang
  • Patent number: D510325
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 4, 2005
    Assignee: ASUSTek Computer Inc.
    Inventors: Chi-Chang Lin, Chih-Yuan Cheng, Heng-Tsung Wang