Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: Methods are disclosed herein for forming conductive patterns having small pitches. An exemplary method includes forming a metal line in a first dielectric layer. The metal line has a first dimension along a first direction and a second dimension along a second direction that is different than the first direction. The method includes forming a patterned mask layer having an opening that exposes a portion of the metal line along an entirety of the second dimension and etching the portion of the metal line exposed by the opening of the patterned mask layer until reaching the first dielectric layer. The metal line is thus separated into a first metal feature and a second metal feature. After removing the patterned mask layer, a barrier layer is deposited over exposed surfaces of the first metal feature and the second metal feature and a second dielectric layer is deposited over the barrier layer.

Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.

Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

Abstract: Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.

Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.

Abstract: A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.

Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.

Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.

Abstract: A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem.

Abstract: A device comprises a first protection layer over sidewalls and a bottom of a first trench in a first dielectric layer, a first barrier layer over the first protection layer, a first metal line in the first trench, a second protection layer over sidewalls and a bottom of a second trench in the first dielectric layer, a second barrier layer over the second protection layer, a second metal line in the first trench, an air gap between the first trench and the second trench and a third protection layer over sidewalls of a third trench in the first dielectric layer, wherein the first protection layer, the second protection layer and the third protection are formed of a same material.

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.