Patents by Inventor Chih-Yuan Yang

Chih-Yuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11444080
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20220223634
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Inventors: Che Wei Yang, Sheng-Chan Li, Tsun-Kai Tsao, Chih-Cheng Shih, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20220216201
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11367387
    Abstract: A method and an image processing device for mura detection on a display are proposed. The method includes the following steps. A compressed DeMura table corresponding to the display panel is obtained. Decompression is performed on the compressed DeMura table to generate a decompressed DeMura table. Upsampling is performed on the decompressed DeMura table to generate a reconstructed DeMura table. Mura compensation is performed on the display panel based on the reconstructed DeMura table.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: June 21, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Wenhui Yu, Xiaoming Bu, Chih-Yuan Yang
  • Publication number: 20220189387
    Abstract: A method and an image processing device for mura detection on a display are proposed. The method includes the following steps. A compressed DeMura table corresponding to the display panel is obtained. Decompression is performed on the compressed DeMura table to generate a decompressed DeMura table. Upsampling is performed on the decompressed DeMura table to generate a reconstructed DeMura table. Mura compensation is performed on the display panel based on the reconstructed DeMura table.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: Novatek Microelectronics Corp.
    Inventors: Wenhui Yu, Xiaoming Bu, Chih-Yuan Yang
  • Patent number: 11358252
    Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
  • Patent number: 11251063
    Abstract: A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jheng-Si Su, Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen-Chieh Lai
  • Publication number: 20210200863
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve feature engineering efficiency.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 1, 2021
    Inventors: Chih-Yuan Yang, Yi Gai
  • Publication number: 20210060728
    Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
  • Publication number: 20210056217
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate electronic data security. An example apparatus includes a data storage including a memory adjusted to store data organized according to a data table including columns identifying a first data record and a first security tag associated with the first data record. In the example apparatus, retrieval of data from the data storage involves a bit operation comparing the first security tag with a first privilege tag. In the example apparatus, the data storage provides the first data record when the bit operation comparing the first security tag with the first privilege tag has a non-zero result, and the data storage does not provide the first data record when the bit operation comparing the first security tag with the first privilege tag has a zero result.
    Type: Application
    Filed: April 9, 2020
    Publication date: February 25, 2021
    Inventors: Chih-Yuan Yang, Yi Gai
  • Patent number: 10915627
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve feature engineering efficiency. An example method disclosed herein includes retrieving a log file in a first file format, the log file containing feature occurrence data, generating a first unit operation based on the first file format to extract the feature occurrence data from the log file to a string, the first unit operation associated with a first metadata tag, generating second unit operations to identify respective features from the feature occurrence data, the second unit operations associated with respective second metadata tags, and generating a first sequence of the first metadata tag and the second metadata tags to create a first vector output file of the feature occurrence data.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: February 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Chih-Yuan Yang, Yi Gai
  • Publication number: 20210028049
    Abstract: A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jheng-Si SU, Yu-Chen WEI, Chih-Yuan YANG, Shih-Ho LIN, Jen-Chieh LAI
  • Publication number: 20200410928
    Abstract: A method of controlling image data includes the steps of: receiving an image frame; generating an image data distribution of the image frame; and controlling a parameter for displaying the image frame according to the image data distribution.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Chih-Yuan Yang, Feng-Ting Pai
  • Patent number: 10861384
    Abstract: A method of controlling image data includes the steps of: receiving an image frame; generating an image data distribution of the image frame; and controlling a parameter for displaying the image frame according to the image data distribution.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 8, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chih-Yuan Yang, Feng-Ting Pai
  • Publication number: 20200372151
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve feature engineering efficiency.
    Type: Application
    Filed: February 28, 2020
    Publication date: November 26, 2020
    Inventors: Chih-Yuan Yang, Yi Gai
  • Patent number: 10843307
    Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
  • Patent number: 10804133
    Abstract: A method for transporting an article used in semiconductor fabrication is provided. The method includes moving a first transporter next to an article to have the article faces a plurality of gas holes formed on the first transporter; suspending the article with the first transporter in a non-contact manner by providing a flow of gas through the gas holes of the first transporter; and transferring the article with the first transporter while the flow of gas is continuously provided.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jheng-Si Su, Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen-Chieh Lai
  • Publication number: 20200238473
    Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yuan YANG, Huai-Tei YANG, Yu-Chen WEI, Szu-Cheng WANG, Li-Hsiang CHAO, Jen-Chieh LAI, Shih-Ho LIN
  • Publication number: 20200175166
    Abstract: A malicious object detection system for use in managed runtime environments includes a check circuit to receive call information generated by an application, such as an Android application. A machine learning circuit coupled to the check circuit applies a machine learning model to assess the information and/or data included in the call and detect the presence of a malicious object, such as malware or a virus, in the application generating the call. The machine learning model may include a global machine learning model distributed across a number of devices, a local machine learning model based on use patterns of a particular device, or combinations thereof. A graphical user interface management circuit halts execution of applications containing malicious objects and generates a user perceptible output.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: Mingwei Zhang, Xiaoning Li, Ravi L. Sahita, Aravind Subramanian, Abhay S. Kanhere, Chih-Yuan Yang, Yi Gai
  • Patent number: 10621370
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate electronic data security. An example apparatus includes a data storage including a memory adjusted to store data organized according to a data table including columns identifying a first data record and a first security tag associated with the first data record. In the example apparatus, retrieval of data from the data storage involves a bit operation comparing the first security tag with a first privilege tag. In the example apparatus, the data storage provides the first data record when the bit operation comparing the first security tag with the first privilege tag has a non-zero result, and the data storage does not provide the first data record when the bit operation comparing the first security tag with the first privilege tag has a zero result.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Chih-Yuan Yang, Yi Gai