Patents by Inventor Chiharu Iriguchi

Chiharu Iriguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8610470
    Abstract: The present invention provides a semiconductor integrated circuit capable of achieving high voltage. The proposed semiconductor integrated circuit includes a first node [VOUT] connected to a first potential node [VDD], and a first n-channel transistor [NT1] and a second n-channel transistor [NT2] serially connected between a first node [VOUT] and a second potential node [VSS] of a lower potential than the first potential node. One end of NT1 is connected to the second potential node [VSS], the other end thereof is connected to one end of the second n-channel transistor [NT2], a gate terminal thereof is connected to a second node [VIN], the other end of NT2 is connected to the first node [VOUT], and a gate terminal thereof is connected to a first intermediate range potential [VM1] positioned between the first potential node [VDD] and the second potential node [VSS].
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: December 17, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7923293
    Abstract: A method for manufacturing a semiconductor device includes: (a) transferring an electronic component that has an electrode and formed on a first substrate from the first substrate to a second substrate; and (b) forming a wiring line electrically coupling the electrode and a terminal on the second substrate. A cavity is provided between the electrode of the electronic component transferred on the second substrate and the second substrate, and the wiring line is formed in the cavity.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: April 12, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Publication number: 20100188144
    Abstract: The present invention provides a semiconductor integrated circuit capable of achieving high voltage. The proposed semiconductor integrated circuit includes a first node [VOUT] connected to a first potential node [VDD], and a first n-channel transistor [NT1] and a second n-channel transistor [NT2] serially connected between a first node [VOUT] and a second potential node [VSS] of a lower potential than the first potential node. One end of NT1 is connected to the second potential node [VSS], the other end thereof is connected to one end of the second n-channel transistor [NT2], a gate terminal thereof is connected to a second node [VIN], the other end of NT2 is connected to the first node [VOUT], and a gate terminal thereof is connected to a first intermediate range potential [VM1] positioned between the first potential node [VDD] and the second potential node [VSS].
    Type: Application
    Filed: December 8, 2009
    Publication date: July 29, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu Iriguchi
  • Patent number: 7750380
    Abstract: A semiconductor device includes a substrate, a first gate electrode, a second gate electrode, a first channel region positioned between the substrate and the first gate electrode, a second channel region positioned between the substrate and the second gate electrode, a gate insulation film positioned at least between the first channel region and the first gate electrode, and between the second channel region and the second gate electrode, a first conducting section, a second conducting section, and a third conducting section each positioned between the substrate and the gate insulation film, and an intermediate electrode electrically connected to the second gate electrode, and overlapping a part of the first gate electrode, wherein the first channel region is positioned between the first conducting section and the second conducting section, and the second channel region is positioned between the second conducting section and the third conducting section.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 6, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7670949
    Abstract: A method of manufacturing a semiconductor device includes: forming a first photosensitive material pattern having an opening hole on a work target layer formed on an active surface of a substrate; performing a first etching by performing an etching treatment to the work target layer using the first photosensitive material pattern as a mask, and forming one of a concave and a groove in a tapered shape with a wide opening to the work target layer while enlarging the opening hole, by performing the etching treatment so as to enlarge the opening hole; and filling a metal film into one of the concave and the groove.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: March 2, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7643188
    Abstract: A method of recording an exposure pattern in a recording layer of a holographic mask, using an original reticle that has the exposure pattern formed therein, the recording method comprising: illuminating a first recording light and a first reference light to the recording layer simultaneously, the first recording light being illuminated through an original reticle placed opposite to the holographic mask with a first gap therebetween, the first reference light being illuminated to the recording layer at a first incident angle; and illuminating a second recording light and a second reference light to the recording layer simultaneously, the second recording light being illuminated through the original reticle placed opposite to the holographic mask with a second gap therebetween, the second gap being different from the first gap, the second reference light being illuminated to the recording layer at a second incident angle.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: January 5, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7547589
    Abstract: The invention provides a technique that enables formation of minute patterns on an uneven substrate in volume production without reducing productivity. The method for fabricating a semiconductor device includes: first patterning a semiconductor film on a substrate to form element regions, each of which will be provided with a source/drain region and a channel region, second forming a gate insulating film covering segments of the patterned semiconductor film in the respective element regions, third forming gate electrodes on the gate insulating film at predetermined positions, and fourth forming the source/drain region and the channel region in each element region. At least the gate electrodes are formed by a process including an exposure step through a holographic exposure mask in the third step, and by a process including an exposure step through a projection exposure mask, the element regions are formed in the first step, and the source/drain regions and the channel regions are formed in the fourth step.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: June 16, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Publication number: 20080179759
    Abstract: A method for manufacturing a semiconductor device includes: (a) transferring an electronic component that has an electrode and formed on a first substrate from the first substrate to a second substrate; and (b) forming a wiring line electrically coupling the electrode and a terminal on the second substrate. A cavity is provided between the electrode of the electronic component transferred on the second substrate and the second substrate, and the wiring line is formed in the cavity.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 31, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Chiharu IRIGUCHI
  • Patent number: 7352442
    Abstract: An aligner to expose any exposure area includes an exposure light source that emits an exposure beam having a specified width to expose the exposure area to light; a douser having a width corresponding to at least the width of the exposure beam; and a shading unit to prevent the exposure beam from reaching an area other than the exposure area by driving the douser to shut off part or all of the exposure beam. The aligner is capable of forming different exposure areas with high density and having a structure suitable to reduce the size of the entire unit.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: April 1, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Publication number: 20070228426
    Abstract: A semiconductor device includes a substrate, a first gate electrode, a second gate electrode, a first channel region positioned between the substrate and the first gate electrode, a second channel region positioned between the substrate and the second gate electrode, a gate insulation film positioned at least between the first channel region and the first gate electrode, and between the second channel region and the second gate electrode, a first conducting section, a second conducting section, and a third conducting section each positioned between the substrate and the gate insulation film, and an intermediate electrode electrically connected to the second gate electrode, and overlapping a part of the first gate electrode, wherein the first channel region is positioned between the first conducting section and the second conducting section, and the second channel region is positioned between the second conducting section and the third conducting section.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 4, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu IRIGUCHI
  • Publication number: 20070229927
    Abstract: A method of recording an exposure pattern in a recording layer of a holographic mask, using an original reticle that has the exposure pattern formed therein, the recording method comprising: illuminating a first recording light and a first reference light to the recording layer simultaneously, the first recording light being illuminated through an original reticle placed opposite to the holographic mask with a first gap therebetween, the first reference light being illuminated to the recording layer at a first incident angle; and illuminating a second recording light and a second reference light to the recording layer simultaneously, the second recording light being illuminated through the original reticle placed opposite to the holographic mask with a second gap therebetween, the second gap being different from the first gap, the second reference light being illuminated to the recording layer at a second incident angle.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 4, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu Iriguchi
  • Publication number: 20070224835
    Abstract: A method of manufacturing a semiconductor device includes: forming a first photosensitive material pattern having an opening hole on a work target layer formed on an active surface of a substrate; performing a first etching by performing an etching treatment to the work target layer using the first photosensitive materialpattern as a mask, and forming one of a concave and a groove in a tapered shape with a wide opening to the work target layer while enlarging the opening hole, by performing the etching treatment so as to enlarge the opening hole; and filling a metal film into one of the concave and the groove.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 27, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu IRIGUCHI
  • Patent number: 7258957
    Abstract: A method for aligning an exposure mask, comprises: using a plurality of hologram masks, on which alignment marks are formed,; aligning position of the hologram masks toward an object, which is exposed and on which alignment marks are also formed, a plurality of times by using both alignment marks, wherein a first straight line connects a first area on the object to be exposed for a pattern exposure with the alignment mark for aligning with a holographic mask that is used in an exposure onto the first area and a second straight line connects the other area, adjacent to the first area, on the object to be exposed for a pattern exposure with the other alignment mark for aligning with a holographic mask that is used in an exposure onto the another area, and the first straight line and the second straight line are intersected each other.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 21, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7255968
    Abstract: A method for aligning an exposure mask comprises: using a plurality of hologram masks, on which an alignment mark is formed; aligning position of the hologram masks toward an object to be exposed and on which an alignment mark is also formed, with a plurality of times by using both alignment marks; and pattern-exposing the object, wherein, while aligning at least three consecutive times, an alignment mark for third time aligning on the object is set in between alignment marks respectively for second time aligning and first time aligning, or at a position on an opposite side to a side in which the alignment mark for second time aligning is located with respect to the alignment mark for first time aligning.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: August 14, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7151044
    Abstract: The invention reduces the size of an element chip and reduces the manufacturing cost in a thin film transistor type display device in which thin film transistors are formed on a first substrate, wiring lines are formed on a second substrate, and the element chip, including one or more thin film transistors, is peeled off from the first substrate and transferred to the second substrate. In the patterning process of the thin film transistors, holographic lithography or a dynamic auto focus system is used, a design rule of 1.0 ?m or less is used, and only a polycrystalline silicon layer and a first metal layer are used as the wiring lines of the element chip.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: December 19, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Mutsumi Kimura, Chiharu Iriguchi
  • Patent number: 7073542
    Abstract: The invention automates determination of the quantity of a index matching liquid.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: July 11, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7049617
    Abstract: In an exposure device 100 having a vertically movable stage device 120, and which performs exposure by projecting a pattern recorded on a hologram mask 130 onto a substrate to be exposed 110 on which is formed a photosensitive material film 112 and which is placed on the above stage device, a film thickness measurement mechanism 160, 162 measures the thickness of the photosensitive material film 112, and based on the measured film thickness a light amount control mechanism 162 controls the amount of exposure light from the exposure light source 140. An appopriate amount of light is set according to the film thickness, so that an accurate pattern can be formed in a single exposure pass.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: May 23, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7046408
    Abstract: Exemplary embodiments of the present invention provide a method of hologram exposure that is capable of making accurate alignment. A method of exposure according to one exemplary aspect of the present invention includes providing a mask for hologram exposure M2 including first alignment marks A1 through A4 that is readable with an alignment optical system 40 and a hologram exposure area D2 to which a hologram is recorded by hologram exposure so as to form a desirable coherent pattern and second alignment marks AL1 through AL4 on a substrate 10.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 16, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Publication number: 20060068304
    Abstract: A method for aligning an exposure mask comprises: using a plurality of hologram masks, on which an alignment mark is formed; aligning position of the hologram masks toward an object to be exposed and on which an alignment mark is also formed, with a plurality of times by using both alignment marks; and pattern-exposing the object, wherein, while aligning at least three consecutive times, an alignment mark for third time aligning on the object is set in between alignment marks respectively for second time aligning and first time aligning, or at a position on an opposite side to a side in which the alignment mark for second time aligning is located with respect to the alignment mark for first time aligning.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 30, 2006
    Applicant: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Publication number: 20060068305
    Abstract: A method for aligning an exposure mask, comprises :using a plurality of hologram masks, on which alignment marks are formed,; aligning position of the hologram masks toward an object, which is exposed and on which alignment marks are also formed, a plurality of times by using both alignment marks, wherein a first straight line connects a first area on the object to be exposed for a pattern exposure with the alignment mark for aligning with a holographic mask that is used in an exposure onto the first area and a second straight line connects the other area, adjacent to the first area, on the object to be exposed for a pattern exposure with the other alignment mark for aligning with a holographic mask that is used in an exposure onto the another area, and the first straight line and the second straight line are intersected each other.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 30, 2006
    Applicant: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi