Patents by Inventor Chiharu Iriguchi

Chiharu Iriguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050063030
    Abstract: Exemplary embodiments of the present invention provide a method of hologram exposure that is capable of making accurate alignment. A method of exposure according to one exemplary aspect of the present invention includes providing a mask for hologram exposure M2 including first alignment marks A1 through A4 that is readable with an alignment optical system 40 and a hologram exposure area D2 to which a hologram is recorded by hologram exposure so as to form a desirable coherent pattern and second alignment marks AL1 through AL4 on a substrate 10.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 24, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu Iriguchi
  • Publication number: 20050026340
    Abstract: The invention provides a technique that enables formation of minute patterns on an uneven substrate in volume production without reducing productivity. The method for fabricating a semiconductor device includes: first patterning a semiconductor film on a substrate to form element regions, each of which will be provided with a source/drain region and a channel region, second forming a gate insulating film covering segments of the patterned semiconductor film in the respective element regions, third forming gate electrodes on the gate insulating film at predetermined positions, and fourth forming the source/drain region and the channel region in each element region. At least the gate electrodes are formed by a process including an exposure step through a holographic exposure mask in the third step, and by a process including an exposure step through a projection exposure mask, the element regions are formed in the first step, and the source/drain regions and the channel regions are formed in the fourth step.
    Type: Application
    Filed: May 7, 2004
    Publication date: February 3, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu Iriguchi
  • Publication number: 20040256622
    Abstract: The invention reduces the size of an element chip and reduces the manufacturing cost in a thin film transistor type display device in which thin film transistors are formed on a first substrate, wiring lines are formed on a second substrate, and the element chip, including one or more thin film transistors, is peeled off from the first substrate and transferred to the second substrate. In the patterning process of the thin film transistors, holographic lithography or a dynamic auto focus system is used, a design rule of 1.0 &mgr;m or less is used, and only a polycrystalline silicon layer and a first metal layer are used as the wiring lines of the element chip.
    Type: Application
    Filed: January 27, 2004
    Publication date: December 23, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mutsumi Kimura, Chiharu Iriguchi
  • Publication number: 20040185353
    Abstract: An aligner to expose any exposure area includes an exposure light source that emits an exposure beam having a specified width to expose the exposure area to light; a douser having a width corresponding to at least the width of the exposure beam; and a shading unit to prevent the exposure beam from reaching an area other than the exposure area by driving the douser to shut off part or all of the exposure beam. The aligner is capable of forming different exposure areas with high density and having a structure suitable to reduce the size of the entire unit.
    Type: Application
    Filed: March 2, 2004
    Publication date: September 23, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu Iriguchi
  • Publication number: 20040103950
    Abstract: [Object] To automate determination of the quantity of a index matching liquid.
    Type: Application
    Filed: March 24, 2003
    Publication date: June 3, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu Iriguchi
  • Patent number: 6707126
    Abstract: A semiconductor device is provided which has high sensitivity and excellent electrical power saving due to a structure in which an element having a pin photodiode and a MOS transistor which are integrated is formed in an SOI substrate or the like. A production method and an electronic device are also provided.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: March 16, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 6690048
    Abstract: A semiconductor device, a manufacturing method, and an electronic apparatus are provided. The semiconductor device comprises elements, each having a photogate for converting light into an electric charge integrated with a MOS transistor for transferring the electric charge, formed in a substrate formed by depositing a semiconductive layer on an insulating layer.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: February 10, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Publication number: 20030203284
    Abstract: The invention forms micropores by an off-axis holographic exposure process.
    Type: Application
    Filed: March 25, 2003
    Publication date: October 30, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Chiharu Iriguchi, Mitsutoshi Miyasaka
  • Publication number: 20030039896
    Abstract: In an exposure device 100 having a vertically movable stage device 120, and which performs exposure by projecting a pattern recorded on a hologram mask 130 onto a substrate to be exposed 110 on which is formed a photosensitive material film 112 and which is placed on the above stage device, a film thickness measurement mechanism 160, 162 measures the thickness of the photosensitive material film 112, and based on the measured film thickness a light amount control mechanism 162 controls the amount of exposure light from the exposure light source 140. An appopriate amount of light is set according to the film thickness, so that an accurate pattern can be formed in a single exposure pass.
    Type: Application
    Filed: July 24, 2002
    Publication date: February 27, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Chiharu Iriguchi
  • Publication number: 20020109165
    Abstract: A semiconductor device, a manufacturing method, and an electronic apparatus are provided. The semiconductor device comprises elements, each having a photogate for converting light into an electric charge integrated with a MOS transistor for transferring the electric charge, formed in a substrate formed by depositing a semiconductive layer on an insulating layer.
    Type: Application
    Filed: November 15, 2001
    Publication date: August 15, 2002
    Inventor: Chiharu Iriguchi
  • Publication number: 20020081766
    Abstract: It is an object to provide a semiconductor device which has high sensitivity and excellent electrical power saving due to a structure in which an element having a pin photodiode and a MOS transistor which are integrated is formed in an SOI substrate or the like, and to provide a production method thereof and an electronic device.
    Type: Application
    Filed: November 14, 2001
    Publication date: June 27, 2002
    Inventor: Chiharu Iriguchi
  • Patent number: 6328904
    Abstract: A method of manufacturing a field emission element comprises steps of: (a) forming a base layer comprising a gate film being capable of chemical reaction accompanied by volume expansion; (b) forming an insulating film on said base layer; (c) forming a taper-shaped first hole in said insulating film; (d) forming a second hole in said gate film by anisotropically etching said gate film using said insulating film as a mask; (e) reacting a part of a surface layer of said gate film to form a volume-expanded film by chemical reaction; (f) forming an emitter film made of an electrically conductive material on said insulating film and said expanded film; and (g) exposing said emitter film and said gate film by removing unnecessary parts comprising said substrate and said expanded film.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: December 11, 2001
    Assignee: Yamaha Corporation
    Inventors: Atsuo Hattori, Chiharu Iriguchi