Patents by Inventor Chih-Hsien Chang
Chih-Hsien Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170343Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: ApplicationFiled: January 24, 2024Publication date: May 23, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Chi-On CHUI, Chih-Chieh YEH, Cheng-Hsien WU, Chih-Sheng CHANG, Tzu-Chiang CHEN, I-Sheng CHEN
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Publication number: 20240171160Abstract: A sensing circuit coupled to a sensor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an oscillator. The first transistor, coupled to a first current source and the sensor, receives a sensing current from the sensor. A gate terminal of the first transistor is connected to a source terminal of the first transistor. The second transistor, coupled to the first transistor and a second current source, generates a first current according to the sensing current. The first current is greater than the sensing current. The third transistor, coupled to the second transistor and the second current source, generates a second current according to the first current. The fourth transistor, coupled to the third transistor, generates a third current. The oscillator is coupled to the fourth transistor. The oscillator generates a signal having an oscillation frequency according to the third current.Type: ApplicationFiled: February 7, 2023Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Tsun Chen, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
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Publication number: 20240170355Abstract: An electronic package is provided, in which an electronic element is disposed on a carrier structure, and an interposer is stacked on the electronic element. Further, a wire is connected to the interposer and grounds the carrier structure, such that the wire and the interposer surround the electronic element. Therefore, the wire can be used as a shielding element when the electronic package is in operation to prevent the electronic element from being subjected to external electromagnetic interference.Type: ApplicationFiled: February 24, 2023Publication date: May 23, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chien-Cheng LIN
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Publication number: 20240170381Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
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Publication number: 20240170415Abstract: An electronic package and a method thereof are provided, in which an electronic component, conductive structures and conductive components are disposed on one side of a carrier and electrically connected to the carrier. The electronic component, the conductive structures and the conductive components are encapsulated by an encapsulation layer. A shielding layer is formed on the encapsulation layer to cover the electronic component, where the shielding layer is electrically connected to the conductive structures and free from being electrically connected to the conductive components. A shielding structure is formed to cover the other side of the carrier.Type: ApplicationFiled: April 11, 2023Publication date: May 23, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chia-Yang CHEN
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Publication number: 20240162308Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.Type: ApplicationFiled: February 9, 2023Publication date: May 16, 2024Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
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Patent number: 11984901Abstract: A counter signal counting at a frequency of a clock signal is generated. Among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio is selected. In response to the counter signal reaching the selected threshold, a logic level of an output signal is switched.Type: GrantFiled: May 31, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen
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Patent number: 11984412Abstract: An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.Type: GrantFiled: January 17, 2023Date of Patent: May 14, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien Chiu, Ko-Wei Chang
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Patent number: 11978511Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.Type: GrantFiled: January 21, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Huei Lee, Chun-Wei Chang, Jian-Hong Lin, Wen-Hsien Kuo, Pei-Chun Liao, Chih-Hung Nien
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Patent number: 11980040Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.Type: GrantFiled: June 14, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
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Publication number: 20240146288Abstract: A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Che LU, Chin-Ming FU, Chih-Hsien CHANG
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Publication number: 20240145403Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.Type: ApplicationFiled: February 6, 2023Publication date: May 2, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
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Patent number: 11974367Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.Type: GrantFiled: October 4, 2022Date of Patent: April 30, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
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Patent number: 11961580Abstract: A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.Type: GrantFiled: June 1, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Che Lu, Chin-Ming Fu, Chih-Hsien Chang
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Publication number: 20240085941Abstract: An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Che Lu, Chin-Ming Fu, Chih-Hsien Chang
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Publication number: 20240088182Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
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Patent number: 11929314Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: GrantFiled: March 12, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 11923252Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: GrantFiled: January 27, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
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Patent number: D1017062Type: GrantFiled: January 27, 2022Date of Patent: March 5, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Chuan-Hsi Chang, Peng-Hui Wang, Ming-Chieh Cheng
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Patent number: D1018891Type: GrantFiled: December 13, 2021Date of Patent: March 19, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Peng-Hui Wang, Ming-Chieh Cheng, Xiu-Yi Lin