Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A method includes receiving a carrier, the carrier including a carrier body, a first filter, and a housing securing the first filter to the carrier body. The method further includes uninstalling the housing from the carrier, replacing the first filter with a second filter, reinstalling the housing on the carrier body, and inspecting the second filter. Inspecting the second filter includes using an automatic inspection mechanism to detect surface flatness of the second filter.

Abstract: The present invention provides a method for preparing an activated carbon, which includes impregnating a carbonaceous material with carbonated water; and exposing the carbonaceous material to microwave radiation to produce the activated carbon.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Abstract: A mounting system for an electronic device is disclosed. The mounting system includes a mounting plate; a plurality of fasteners for coupling the mounting plate with the electronic device; a single main gear mounted on the mounting plate; a plurality of secondary gears coupled, respectively, to the plurality of fasteners; and a plurality of intermediate gears mounted on the mounting plate and rotationally coupled between the single main gear and the plurality of secondary gears. Rotation of each of the plurality of secondary gears causes a fastening movement of a respective one of the plurality of fasteners. Simultaneous rotation of the plurality of intermediate gears causes the plurality of secondary gears to rotate simultaneously in response to a single rotational force being received by the main gear. The simultaneous rotation of the plurality of intermediate gears causes a simultaneous fastening movement of the plurality of secondary gears.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: An electronic device manufacturing system configured to obtain current sensor data associated with a sensor of a substrate manufacturing system and determine a slope value associated with the current sensor data. Responsive to determining that the slope value satisfied a threshold criterion associated with a fault detection limit, at least one of an alert is generated or a corrective action performed.

Abstract: A formable stopper applied to a fixing structure comprises a body having an assembly hole or an assembly section. The assembly hole or the assembly section includes a placement portion and an assembly portion. The assembly portion is in communication with or connected to the placement portion, or the placement portion is the assembly portion. The formable stopper further comprises a formable body. The formable body is adapted to be extruded, placed, or fitted into the placement portion, and extruded, placed, or fitted into the assembly portion, so as to form an interference structure or to form an interference force for preventing or avoiding the formable body from falling out of the assembly hole.

Abstract: A method includes forming a database, finding a plurality of dicing marks on a wafer, wherein patterns of the plurality of dicing marks match a pattern in the database, measuring a die pitch of the wafer according to a patch of adjacent two of the plurality of dicing marks, and determining kerf centers of the wafer based on the plurality of dicing marks. The measuring the die pitch and the determining the kerf centers are performed on a same wafer-holding platform. The wafer is diced into a plurality of dies, and the dicing is performed aligning to the kerf centers.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

Abstract: A circuit layout checking method includes: determining whether there is only a first layout pattern and/or a second layout pattern corresponding to a filler cell or a second gate array cell exist in a region extending outward from the first layout pattern corresponding to a first gate array cell; determining whether a first pattern corresponding to an electrical connection layer in the first layout pattern is enclosed by a second pattern corresponding to a metal layer in the first layout pattern and whether each spacing between all boundaries of the first pattern and those of the second pattern is not less than a predetermined distance; and if there is only the first and/or second layout patterns in the first region and if the first pattern is enclosed by the second pattern and each spacing is not less than the predetermined distance, generating data indicating layout design of an integrated circuit.

Abstract: A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.

Abstract: A package and a method of manufacturing the same are provided. The package includes a first die, a second die, a third die, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The third die is disposed on the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the third die and fills in a gap between the first die, the second die, and the third die. The RDL structure is disposed on the third die and the encapsulant.

Abstract: A semiconductor arrangement includes a heat source above an interconnect layer and below a heat conductor. The heat conductor is coupled to a heat sink by a thermally conductive bonding layer. Heat from the heat source is conducted through the heat conductor in a direction opposite the direction of the interconnect layer, through the thermally conductive bonding layer, and to a heat sink. The heat conductor includes an arrangement of dielectric layers, dummy metal layers, and dummy VIA layers.

Abstract: A computing system includes a chassis, a water circulation network coupled to the chassis, a power distribution network coupled to the chassis, and one or more sleds removably coupled to the chassis. The water circulation network includes a cold water distribution network and a hot water collection network. Each sled of the one or more sleds includes a corresponding cold plate. Each sled is configured to slide along the chassis in two slide directions including a slide-close direction to reach a closed position and a slide-open direction to vacate the closed position. When in the closed position, each sled is configured to (a) bridge the hot water collection network and the cold water distribution network via the corresponding cold plate and (b) couple to the power distribution network.

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.