Patents by Inventor Chih-Wei Lin
Chih-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12690241Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.Type: GrantFiled: October 17, 2022Date of Patent: July 21, 2026Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tse-Hsiao Liu, Chih-Wei Lin, Po-Hao Chiu, Pi-Kuang Chuang, Ching-Yi Hsu
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Publication number: 20260158101Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: March 6, 2025Publication date: June 11, 2026Applicant: AbbVie Inc.Inventors: Walid M. Awni, Barry M. Bernstein, Andrew L. Campbell, Sandeep Dutta, Chih-Wei Lin, Wei Liu, Rajeev M. Menon, Thomas J. Podsadecki, Tianli Wang, Sven Mensing
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Publication number: 20260144125Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.Type: ApplicationFiled: April 14, 2025Publication date: May 21, 2026Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20260090476Abstract: A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules.Type: ApplicationFiled: November 25, 2025Publication date: March 26, 2026Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chun-Cheng Lin, Chih-Wei Lin, Yi-Da Tsai, Hsaing-Pin Kuan, Chih-Chiang Tsao, Hsuan-Ting Kuo, Hsiu-Jen Lin, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh
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Patent number: 12568854Abstract: A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.Type: GrantFiled: February 17, 2022Date of Patent: March 3, 2026Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Fung Chang, Sheng-Feng Weng, Ming-Yu Yen, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 12512451Abstract: A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules.Type: GrantFiled: August 8, 2022Date of Patent: December 30, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chun-Cheng Lin, Chih-Wei Lin, Yi-Da Tsai, Hsaing-Pin Kuan, Chih-Chiang Tsao, Hsuan-Ting Kuo, Hsiu-Jen Lin, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh
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Patent number: 12512419Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: GrantFiled: November 6, 2023Date of Patent: December 30, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 12512384Abstract: A semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. The semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. The electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally coupled to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.Type: GrantFiled: July 29, 2022Date of Patent: December 30, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Fung Chang, Sheng-Feng Weng, Ming-Yu Yen, Kai-Ming Chiang, Wei-Jhan Tsai, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 12489030Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: GrantFiled: January 4, 2024Date of Patent: December 2, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 12487390Abstract: A polarizer applied for a viewing side of a display is disclosed. The polarizer comprises a polarizing layer with an absorption axis, and a protective film disposed on the viewing side surface of the polarizing layer. The protective film includes a birefringent substrate adjacent to the polarizing layer having a birefringence difference not greater than 0.10 and having a slow axis and a fast axis perpendicular to each other, wherein the slow axis is parallel to the absorption axis of the polarizing layer, and an interference elimination layer disposed on a display side surface of the birefringent substrate, wherein the interference elimination layer has a diffusing layer disposed on the birefringent substrate, and a refractive-index-matching layer disposed on the diffusing layer, wherein with the total haze of the protective film is between 30% and 75% and the reflectivity of the protective film satisfies the relationship (RSCI?RSCE)?1.0% and RSCE/(RSCI?RSCE)?1.Type: GrantFiled: April 10, 2023Date of Patent: December 2, 2025Assignee: BenQ Materials CorporationInventors: Yu-Wei Tu, Chih-Wei Lin, Kuo-Hsuan Yu
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Publication number: 20250349808Abstract: A package includes a first redistribution structure, a first die, a second die, a bridge structure, and an encapsulant. The first redistribution structure has a first side and a second side opposite to the first side. The first die and the second die are disposed on the first side of the first redistribution structure. The bridge structure is disposed on the second side of the first redistribution structure. The bridge structure includes routing patterns and connectors disposed on the routing patterns. A lateral dimension of the bridge structure is smaller than a lateral dimension of the first redistribution structure. The encapsulant is disposed on the second side of the first redistribution structure. The routing patterns and the connectors of the bridge structure are completely spaced apart from the encapsulant. The encapsulant is in physical contact with sidewalls of the bridge structure.Type: ApplicationFiled: July 23, 2025Publication date: November 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Publication number: 20250349572Abstract: A pickup apparatus for separating a semiconductor package from an adhesive film includes a platform, a roller, a moving mechanism, and a collector element. The platform has a surface disposed with the adhesive film, where the adhesive film is disposed between the platform and the semiconductor package. The roller is disposed inside the platform and under the adhesive film, where the roller includes a body and a plurality of protrusions distributed over the body. The moving mechanism is connected to the roller to control a movement of the roller. The collector element is disposed over the platform and the adhesive film, where the collector element is configured to remove the semiconductor package from the adhesive film.Type: ApplicationFiled: July 24, 2025Publication date: November 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chun Liao, Ching-Hua Hsieh, Chih-Wei Lin, Hsiao-Chung Liang, Ying-Jui Huang
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Publication number: 20250349799Abstract: A method includes following steps. A first semiconductor device is provided, wherein the first semiconductor device includes a semiconductor substrate, a plurality of first dies and a second die surrounded by the first dies, and the first dies and the second die are formed over the semiconductor substrate. The first semiconductor device is bonded to a first substrate through the first dies, to seal an enclosed cavity among inner sidewalls of the first dies, a surface of the first substrate and a surface of the semiconductor substrate and form a gap between the second die and the first substrate.Type: ApplicationFiled: July 23, 2025Publication date: November 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Fung Chang, Sheng-Feng Weng, Ming-Yu Yen, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20250350169Abstract: A motor structure includes a stator ring, a rotor, a wind blade set and a thermally-conductive casing. The stator ring has a rotor accommodation space located therein. The rotor is located in the rotor accommodation space. The wind blade set is arranged at one side of the rotor. The thermally-conductive casing encloses the stator ring, rotor and wind blade set. The thermally-conductive casing includes a thermally-conductive cover, and the thermally-conductive cover has a plurality of radially-inner holes and a plurality of radially-outer holes.Type: ApplicationFiled: August 2, 2024Publication date: November 13, 2025Inventors: Wan-Bao SHEN, Chih-Wei LIN, Chia-Feng WU
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Patent number: 12471225Abstract: A multi-node computing system is disclosed. The multi-node computing system includes a chassis and a detachable cable cage removably mounted within the chassis. The detachable cable cage includes a base frame assembly having a bottom plate connecting a first plate and a second plate. The first and second plate face each other and extend across a width of the base frame assembly between a first side and a second side of the base frame assembly. The detachable cable cage further includes a first panel assembly movingly coupled to the first side of the base frame assembly and a second panel assembly movingly coupled to the second side of the base frame assembly. The first panel assembly and/or the second panel assembly is movable between a closed position and an open position, and an internal space of the detachable cable cage is accessible in the open position.Type: GrantFiled: February 23, 2023Date of Patent: November 11, 2025Assignee: QUANTA COMPUTER INC.Inventors: Chao-Jung Chen, Chih-Wei Lin, Chin-Chu Chen, Ming-Yuan Hung
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Publication number: 20250343078Abstract: A method includes forming a database, finding a plurality of dicing marks on a wafer, wherein patterns of the plurality of dicing marks match a pattern in the database, measuring a die pitch of the wafer according to a patch of adjacent two of the plurality of dicing marks, and determining kerf centers of the wafer based on the plurality of dicing marks. The measuring the die pitch and the determining the kerf centers are performed on a same wafer-holding platform. The wafer is diced into a plurality of dies, and the dicing is performed aligning to the kerf centers.Type: ApplicationFiled: July 11, 2025Publication date: November 6, 2025Inventors: Jen-Chun Liao, Chih-Wei Lin, Ching-Hua Hsieh, Wen-Chih Chiou
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Patent number: 12463067Abstract: A pickup apparatus for separating a semiconductor package from an adhesive film includes a platform, a roller, a moving mechanism, and a collector element. The platform has a surface disposed with the adhesive film, where the adhesive film is disposed between the platform and the semiconductor package. The roller is disposed inside the platform and under the adhesive film, where the roller includes a body and a plurality of protrusions distributed over the body. The moving mechanism is connected to the roller to control a movement of the roller. The collector element is disposed over the platform and the adhesive film, where the collector element is configured to remove the semiconductor package from the adhesive film.Type: GrantFiled: March 8, 2023Date of Patent: November 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chun Liao, Ching-Hua Hsieh, Chih-Wei Lin, Hsiao-Chung Liang, Ying-Jui Huang
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Publication number: 20250323192Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.Type: ApplicationFiled: June 25, 2025Publication date: October 16, 2025Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 12444719Abstract: A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.Type: GrantFiled: June 6, 2024Date of Patent: October 14, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Patent number: 12438007Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.Type: GrantFiled: March 21, 2022Date of Patent: October 7, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Sung Huang, Tsung-Hsien Chiang, Ming Hung Tseng, Hao-Yi Tsai, Yu-Hsiang Hu, Chih-Wei Lin, Lipu Kris Chuang, Wei Lun Tsai, Kai-Ming Chiang, Ching Yao Lin, Chao-Wei Li, Ching-Hua Hsieh