Patents by Inventor Chih-Yuan Hou

Chih-Yuan Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12154892
    Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.
    Type: Grant
    Filed: December 6, 2023
    Date of Patent: November 26, 2024
    Assignee: AUO Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Publication number: 20240387787
    Abstract: A display apparatus includes a light-transmitting substrate, a pad group, a mini-IC, a first wire, and a first light-emitting element. The pad group includes a first pad, a second pad, and a third pad. The mini-IC is bonded to the pad group. The first wire is electrically connected to the first pad. The first pad and the second pad have first sides and second sides opposite to each other. The third pad is located on the first sides of the first pad and the second pad. The first wire is structurally separated from the second pad and the third pad. A winding segment of the first wire is disposed between the second pad and the third pad and bypasses the second pad from the first sides of the first pad and the second pad so as to extend toward the second sides of the first pad and the second pad.
    Type: Application
    Filed: November 30, 2023
    Publication date: November 21, 2024
    Applicant: AUO Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Patent number: 12132156
    Abstract: A display device includes a flexible substrate, a bonding pad, a light-emitting diode, an encapsulant, and a support structure. The bonding pad and the light-emitting diode are located on the flexible substrate. The encapsulant covers the light-emitting diode. The support structure is laterally located between the light-emitting diode and the bonding pad. The support structure has an inclined surface, and a thickness of the support structure close to the light-emitting diode is greater than the thickness of the support structure close to the bonding pad.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 29, 2024
    Assignee: Au Optronics Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Publication number: 20240343643
    Abstract: This invention discloses a synthetic gypsum and gypsum boards produced therefrom. Limestone (Calcium Carbonate), slaked lime (calcium hydroxide), water, and sulfuric acid are mixed, and alpha hemihydrate gypsum is optionally added as crystal seed to produce synthetic gypsum. The synthetic gypsum is then used to make gypsum boards. The gypsum board produced according to this invention contains at least 10% alpha hemihydrate gypsum.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: Feng-Shuo HSU, Chih-Yuan HOU
  • Publication number: 20240105696
    Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Applicant: AUO Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Patent number: 11876086
    Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: January 16, 2024
    Assignee: Au Optronics Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Publication number: 20220367767
    Abstract: A display device includes a flexible substrate, a bonding pad, a light-emitting diode, an encapsulant, and a support structure. The bonding pad and the light-emitting diode are located on the flexible substrate. The encapsulant covers the light-emitting diode. The support structure is laterally located between the light-emitting diode and the bonding pad. The support structure has an inclined surface, and a thickness of the support structure close to the light-emitting diode is greater than the thickness of the support structure close to the bonding pad.
    Type: Application
    Filed: October 27, 2021
    Publication date: November 17, 2022
    Applicant: Au Optronics Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Publication number: 20220302174
    Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.
    Type: Application
    Filed: November 1, 2021
    Publication date: September 22, 2022
    Applicant: Au Optronics Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Patent number: 10879218
    Abstract: A method of manufacturing a display device includes the following steps. A bonding pad is formed on a dielectric layer. A light-shielding material is formed on the dielectric layer. A temperature of the light-shielding material is increased such that the light-shielding material is cured into a light-shielding layer. During curing the light-shielding material into the light-shielding layer, the light-shielding material flows to and contacts a portion of a surface of the bonding pad. A light-emitting element is electrically connected to the bonding pad.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 29, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Publication number: 20200373281
    Abstract: A method of manufacturing a display device includes the following steps. A bonding pad is formed on a dielectric layer. A light-shielding material is formed on the dielectric layer. A temperature of the light-shielding material is increased such that the light-shielding material is cured into a light-shielding layer. During curing the light-shielding material into the light-shielding layer, the light-shielding material flows to and contacts a portion of a surface of the bonding pad. A light-emitting element is electrically connected to the bonding pad.
    Type: Application
    Filed: December 2, 2019
    Publication date: November 26, 2020
    Inventors: Cheng-He RUAN, Jian-Jhou TSENG, Chih-Yuan HOU
  • Patent number: 9748395
    Abstract: A thin film transistor includes a substrate, a gate electrode disposed on the substrate, a channel layer located on the gate electrode, a gate insulation layer disposed between the gate electrode and the channel layer, an etching stop layer disposed on the channel layer, and a source electrode and a drain electrode disposed on the etching stop layer. The gate electrode has multiple through holes, the etching stop layer has multiple contact holes overlapped with the through holes in a direction perpendicular to the substrate, and the source and drain electrodes are respectively electrically connected to the channel layer through the contact holes. A method of manufacturing the thin film transistor, where the contact holes in the etching stop layer are formed by backside exposure using the gate electrode as a mask. A conductivity of a region of the channel layer exposed by the contact holes has a great conductivity.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: August 29, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Chih-Yuan Hou
  • Publication number: 20170110570
    Abstract: A thin film transistor includes a substrate, a gate electrode disposed on the substrate, a channel layer located on the gate electrode, a gate insulation layer disposed between the gate electrode and the channel layer, an etching stop layer disposed on the channel layer, and a source electrode and a drain electrode disposed on the etching stop layer. The gate electrode has multiple through holes, the etching stop layer has multiple contact holes overlapped with the through holes in a direction perpendicular to the substrate, and the source and drain electrodes are respectively electrically connected to the channel layer through the contact holes. A method of manufacturing the thin film transistor, where the contact holes in the etching stop layer are formed by backside exposure using the gate electrode as a mask. A conductivity of a region of the channel layer exposed by the contact holes has a great conductivity.
    Type: Application
    Filed: August 23, 2016
    Publication date: April 20, 2017
    Inventor: Chih-Yuan HOU
  • Patent number: 9513523
    Abstract: A thin film transistor (TFT) array substrate includes a first substrate, a plurality of TFTs formed on the first substrate, a color filter layer covered on the TFTs, and a plurality of pixel electrodes corresponding to the TFTs. The color filter layer is directly formed on the TFTs. The color filter layer includes a plurality of photoresist units. Each of the pixel electrodes is to electrically connected to a drain of the TFT via an opening.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: December 6, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Mei-Ling Wu, Chih-Yuan Hou, Hsin-An Cheng, Yang-Chu Lin
  • Publication number: 20160187689
    Abstract: A thin film transistor (TFT) array substrate includes a first substrate, a plurality of TFTs formed on the first substrate, a color filter layer covered on the TFTs, and a plurality of pixel electrodes corresponding to the TFTs. The color filter layer is directly formed on the TFTs. The color filter layer includes a plurality of photoresist units. Each of the pixel electrodes is to electrically connected to a drain of the TFT via an opening.
    Type: Application
    Filed: July 29, 2015
    Publication date: June 30, 2016
    Applicant: YE XIN TECHNOLOGY CONSULTING CO., LTD.
    Inventors: MEI-LING WU, CHIH-YUAN HOU, HSIN-AN CHENG, YANG-CHU LIN
  • Publication number: 20130250540
    Abstract: A shielding shell includes a frame having a ring-shaped bracket with a receiving chamber therein. The bracket is erected on a printed circuit board with electronic components located in the receiving chamber. A top periphery of the bracket bends inward to form a support eave. At least three restricting portions of inverted-L shape protrude upward and inward at a rear and two symmetrical sides of the top periphery of the bracket respectively. An inserting slot is formed between the restricting portion and the support eave. A cover has a cover plate movably located on the support eave through a front of the frame and further pushed rearward to be inserted in the inserting slots so as to removably cover up the receiving chamber.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Inventor: Chih-Yuan Hou
  • Patent number: 8309442
    Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (?-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the ?-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the ?-Si layer, wherein interface defects existing between the ?-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 13, 2012
    Assignee: Au Optronics Corporation
    Inventor: Chih-Yuan Hou
  • Publication number: 20120202339
    Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (?-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the ?-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the ?-Si layer, wherein interface defects existing between the ?-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.
    Type: Application
    Filed: April 10, 2012
    Publication date: August 9, 2012
    Applicant: Au Optronics Corporation
    Inventor: Chih-Yuan Hou
  • Patent number: 8188470
    Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Au Optronics Corporation
    Inventor: Chih-Yuan Hou
  • Publication number: 20110164674
    Abstract: A multimedia communication system includes: an intercom device operable for picking up audio information, and for performing encoding and modulation processes upon the audio information so as to generate a modulated signal; and a multimedia device coupled to the intercom device for receiving the modulated signal therefrom, and operable for performing demodulation and decoding processes upon the modulated signal so as to generate a decoded audio signal, for generating an output audio signal from external audio information contained in an external input signal when the decoded audio signal is not received thereby, for generating the output audio signal from at least the decoded audio signal when the decoded audio signal and the external input signal are received thereby, and for audible reproduction of the output audio signal.
    Type: Application
    Filed: January 3, 2011
    Publication date: July 7, 2011
    Applicant: LITE-ON TECHNOLOGY CORP.
    Inventors: CHIH-YUAN HOU, TSAO-TENG TSENG, CHI-WEN CHEN
  • Publication number: 20100258800
    Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.
    Type: Application
    Filed: October 6, 2009
    Publication date: October 14, 2010
    Applicant: Au Optronics Corporation
    Inventor: Chih-Yuan Hou