Patents by Inventor Chii-Ming Wu

Chii-Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081563
    Abstract: Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yan-Ming Tsai, Wei-Jung Lin, Fang-Cheng Chen, Chii-Ming Wu
  • Publication number: 20210202301
    Abstract: A method includes forming a first trench in a semiconductor substrate. A mask is filled in the first trench and over the semiconductor substrate. After filling the mask in the first trench, the mask is patterned to form an opening in the mask. A second trench is formed in the semiconductor substrate. A depth of the second trench is different from a depth of the first trench. After forming the second trench in the semiconductor substrate, the mask is removed. A dielectric material is filled in both the first and second trenches.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta WU, Chii-Ming WU, Sen-Hong SYUE, Cheng-Po CHAU
  • Publication number: 20210202809
    Abstract: A semiconductor structure is provided. The semiconductor structure includes metallization structure, a plurality of conductive pads, and a dielectric layer. The plurality of conductive pads is over the metallization structure. The dielectric layer is on the metallization structure and covers the conductive pad. The dielectric layer includes a first dielectric film, a second dielectric film, and a third dielectric film. The first dielectric film is on the conductive pad. The second dielectric film is on the first dielectric film. The third dielectric film is on the second dielectric film. The a refractive index of the first dielectric film is smaller than a refractive index of the second dielectric film, and the refractive index of the second dielectric film is smaller than a refractive index of the third dielectric film.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: CHIA-HUA LIN, YAO-WEN CHANG, CHII-MING WU, CHENG-YUAN TSAI, EUGENE I-CHUN CHEN, TZU-CHUNG TSAI
  • Publication number: 20210159407
    Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 27, 2021
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • Publication number: 20210135102
    Abstract: A semiconductor memory structure includes a memory cell, an encapsulation layer over a sidewall of the memory cell, and a nucleation layer between the sidewall of the memory cell and the encapsulation layer. The memory cell includes a top electrode, a bottom electrode and a data-storage element sandwiched between the bottom electrode and the top electrode. The nucleation layer includes metal oxide.
    Type: Application
    Filed: April 9, 2020
    Publication date: May 6, 2021
    Inventors: HSING-LIEN LIN, FU-TING SUNG, CHING JU YANG, CHII-MING WU
  • Publication number: 20210098398
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Julie Yang, Chii-Ming Wu, Tzu-Chung Tsai, Yao-Wen Chang
  • Publication number: 20210091169
    Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Chia-Shiung Tsai, Chung-Yi Yu, Rei-Lin Chu
  • Patent number: 10950490
    Abstract: A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The semiconductor substrate has a memory device region and a logic core region. The first fin is in the memory device region of the semiconductor substrate. The second fin is in the logic core region of the semiconductor substrate. The first isolation structure is around the first fin. The second isolation structure is around the second fin, and a thickness of the first isolation structure is different from a thickness of the second isolation structure.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Sen-Hong Syue, Cheng-Po Chau
  • Publication number: 20210074805
    Abstract: Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Hai-Dang Trinh, Fa-Shen Jiang
  • Publication number: 20210066587
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.
    Type: Application
    Filed: February 12, 2020
    Publication date: March 4, 2021
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Cheng-Yuan Tsai, Tzu-Chung Tsai, Fa-Shen Jiang
  • Publication number: 20210066591
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 4, 2021
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Tzu-Chung Tsai, Fa-Shen Jiang, Bi-Shen Lee
  • Patent number: 10910560
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnect layers and a diffusion barrier layer is arranged over the bottom electrode. A data storage layer is separated from the bottom electrode by the diffusion barrier layer. A top electrode is over the data storage layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • Publication number: 20210005487
    Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing, and a carrier wafer is on the wafer chuck. A structure that is used for deposition processes is arranged at a top of the housing. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of the structure used for deposition processes within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.
    Type: Application
    Filed: June 22, 2020
    Publication date: January 7, 2021
    Inventors: Tzu-Chung Tsai, Chii-Ming Wu, Hai-Dang Trinh
  • Publication number: 20200411758
    Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: December 31, 2020
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Fa-Shen Jiang
  • Patent number: 10879354
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric feature and an epitaxy feature. The epitaxy feature is on the semiconductor substrate. The epitaxy feature has a top central portion and a corner portion. The dielectric feature is closer to the corner portion than the top central portion, and the corner portion has an impurity concentration higher than that of the top central portion.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chii-Ming Wu, Cheng-Ta Wu
  • Patent number: 10868247
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Chii-Ming Wu, Cheng-Yuan Tsai
  • Publication number: 20200377997
    Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Shing-Chyang Pan
  • Patent number: 10818544
    Abstract: The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC comprises a via dielectric layer, an adhesion layer, and a first electrode. The adhesion layer overlies the via dielectric layer, and the first electrode overlies and directly contacts the adhesion layer. The adhesion layer has a first surface energy at an interface at which the first electrode contacts the adhesion layer, and the first electrode has a second surface energy at the interface. Further, the first surface energy is greater than the second surface energy to promote adhesion. The present disclosure also relates to a method for forming the IC.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Hai-Dang Trinh, Fa-Shen Jiang
  • Publication number: 20200295193
    Abstract: A semiconductor device includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material. The ILD further includes a second portion doped with a large species material, wherein the second portion includes a first sidewall substantially perpendicular to a top surface of the substrate, and the second portion includes a second sidewall having a positive angle with respect to the first sidewall.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Cheng-Ta WU, Chii-Ming WU, Shiu-Ko JANGJIAN, Kun-Tzu LIN, Lan-Fang CHANG
  • Publication number: 20200274058
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Chii-Ming Wu, Cheng-Yuan Tsai