Abstract: A humidifier includes a housing, a humidifying rotor, and an irradiator. The housing is formed with an air passage through which air passes and a water storage tank configured to store water. The humidifying rotor extends over the air passage and the water storage tank. The humidifying rotor rotates so that a portion of the humidifying rotor having absorbed moisture from the water storage tank moves to the air passage and releases the moisture. The irradiator irradiates part of the humidifying rotor with ultraviolet light.

Abstract: An ultraviolet ray radiation apparatus includes a light emitter, a light receiver, and a protector. The light emitter emits ultraviolet light. The light receiver outputs a signal varying with an amount of light received. The protector protects the light receiver from ultraviolet light.

Abstract: An air-conditioning apparatus includes an irradiation device including an LED configured to emit an ultraviolet ray; and includes a heat-dissipating unit configured to dissipate heat of the irradiation device into air.

Abstract: A stratum corneum-collecting adhesive composition includes a hydrophobic component having adhesiveness, and a hydrophilic component that is present in a dispersed state in the hydrophobic component.

Abstract: According to one embodiment, a semiconductor memory includes a first bit line; a second bit line; a source line; a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor; a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor; a third transistor electrically connected to the source line; and a sense amplifier circuit including a first node electrically connected to the first bit line and a second node electrically connected to the second bit line.

Abstract: According to one embodiment, a semiconductor memory includes a first bit line; a second bit line; a source line; a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor; a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor; a third transistor electrically connected to the source line; and a sense amplifier circuit including a first node electrically connected to the first bit line and a second node electrically connected to the second bit line.

Abstract: A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.

Abstract: According to one embodiment, the computing device includes a modeling processing unit configured to model characteristics of selected cell transistor and to define a non-selected cell transistor as a parasitic resistance component of the selected cell transistor. The computing device further includes a computation processing unit configured to use as a parameter a distance between both ends of an active region of the selected cell transistor, and further to store threshold characteristics of the selected cell transistor present in the memory string as a parameter, and to obtain electrical characteristics of the selected cell transistor. The computing device is used for a circuit simulation of a semiconductor memory device including memory string of a plurality of cell transistors connected to one another in series in a channel direction.

Abstract: A semiconductor memory includes a first and a second transistor each with one of source/drain connected to a first wiring. The other of the source/drain for each of first and second transistor is connected to the gate of the other transistor. A third and a fourth transistor each have gates connected to a second wiring, one of source/drain of each connected to a third or fifth wiring, the other of the source/drain connected to the other of the source/drain of the first or second transistor. For the third transistor, a gate insulation layer includes a first ferroelectric material. For the fourth transistor, and a gate insulation layer includes a second ferroelectric material.

Abstract: A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.

Abstract: According to an embodiment, a semiconductor device includes M write word lines, M read word lines, N write bit lines, N read bit lines, N source lines, and M×N cells. The M×N cells are arranged in a matrix including M rows×N columns. A cell in an m-th row×an n-th column includes a first FET, a second FET, and a capacitor. The first FET is connected to an m-th write word line at a gate, to an n-th write bit line at a drain, and to a source of the second FET at a source. The second FET is connected to an m-th read word line at a gate and to an n-th read bit line at a drain. The capacitor is connected to an n-th source line at one end and to the source of the first RET at the other end.

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.

Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.

Abstract: A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.

Abstract: A semiconductor memory includes a first and a second transistor each with one of source/drain connected to a first wiring. The other of the source/drain for each of first and second transistor is connected to the gate of the other transistor. A third and a fourth transistor each have gates connected to a second wiring, one of source/drain of each connected to a third or fifth wiring, the other of the source/drain connected to the other of the source/drain of the first or second transistor. For the third transistor, a gate insulation layer includes a first ferroelectric material. For the fourth transistor, and a gate insulation layer includes a second ferroelectric material.

Abstract: A semiconductor memory device of an embodiment includes a memory cell array. The memory cell array comprises: a semiconductor layer extending in a first direction; a plurality of conductive layers that face a side surface of the semiconductor layer and are stacked in the first direction; a variable resistance film provided at an intersection of the semiconductor layer and one of the conductive layers; a plurality of contact parts provided at ends of the plurality of conductive layers in a second direction intersecting the first direction, respectively; and a plurality of conductive parts that extend in the first direction and are connected to the plurality of contact parts, respectively. At least one of the plurality of contact parts includes a projection part projecting in the second direction.

Abstract: To provide a novel furanone derivative, and a medicine including the same.