Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: A semiconductor device comprises a package board, a first semiconductor chip which is rectangular in shape, has a plurality of first pads arranged along its short side and is placed on the package board, and a second semiconductor chip which is rectangular in shape, has a plurality of second pads arranged along its short side and is placed on the first semiconductor chip so that a vertex of the second semiconductor chip at which its long side and its short side along which no pads are arranged meet falls on a vertex of the first semiconductor chip at which its long side and its short side along which no pads are arranged, and the long sides of the first and second semiconductor chips intersect each other.

Abstract: An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range.

Abstract: A layer defining unit defines different layer numbers to oblique wiring diagrams and via cell diagrams which are included in layout data of a semiconductor integrated circuit design. A first diagram blending unit fetches diagram data including the oblique wiring diagrams and the via cell diagrams from the layout data, synthesizes the diagrams every same layer number, and blends them in overlapped portions. An oblique wiring verifying unit verifies an interval between the oblique wiring diagrams blended by the first diagram blending unit by an allowable minimum interval value S. A second diagram blending unit synthesizes the verified oblique wiring diagram and the via mat diagram of the via cell, thereby forming an oblique wiring mask diagram blended in an overlapped portion.

Abstract: An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range.

Abstract: A layer defining unit defines different layer numbers to oblique wiring diagrams and via cell diagrams which are included in layout data of a semiconductor integrated circuit design. A first diagram blending unit fetches diagram data including the oblique wiring diagrams and the via cell diagrams from the layout data, synthesizes the diagrams every same layer number, and blends them in overlapped portions. An oblique wiring verifying unit verifies an interval between the oblique wiring diagrams blended by the first diagram blending unit by an allowable minimum interval value S. A second diagram blending unit synthesizes the verified oblique wiring diagram and the via mat diagram of the via cell, thereby forming an oblique wiring mask diagram blended in an overlapped portion.