Patents by Inventor Chikage Noritake

Chikage Noritake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050233568
    Abstract: A method for manufacturing a semiconductor device having a solder layer includes the steps of: grinding a mounting surface of a semiconductor chip; etching the mounting surface of the chip; forming an electrode on the mounting surface of the chip; assembling the chip, the solder layer and a base in this order; and heating the chip, the solder layer and the base to be equal to or higher than a solidus temperature of the solder layer so that the solder layer is reflowed for soldering the chip on the base.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 20, 2005
    Inventors: Chikage Noritake, Yoshitsugu Sakamoto, Akira Tanahashi, Hideki Okada, Tomomasa Yoshida
  • Patent number: 6927167
    Abstract: A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: August 9, 2005
    Assignee: Denso Corporation
    Inventors: Yutaka Fukuda, Naohiko Hirano, Chikage Noritake, Shoji Miura
  • Publication number: 20040119088
    Abstract: A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicant: DENSO CORPORATION
    Inventors: Yutaka Fukuda, Naohiko Hirano, Chikage Noritake, Shoji Miura
  • Publication number: 20030119281
    Abstract: A semiconductor device, which has a relatively low ON resistance, is manufactured using the following steps. First, a semiconductor wafer that includes a semiconductor layer and a semiconductor element layer, which is located on the semiconductor layer, is formed. Then, the wafer is ground evenly to a predetermined thickness from the side where the semiconductor layer is located. Next, the wafer is etched to a predetermined thickness from the side where the semiconductor layer is located while the periphery of the wafer is masked against the etchant to form a rim at the periphery. The wafer is reinforced by the rim at the periphery, so even if the wafer is relatively large, the wafer is prevented from breaking or warping at the later steps after the wafer is thinned by etching.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 26, 2003
    Inventors: Mikimasa Suzuki, Chikage Noritake
  • Publication number: 20030022464
    Abstract: A semiconductor device includes a semiconductor chip that generates heat in operation, a pair of heat sinks for cooling the chip, and a mold resin, in which the chip and the heat sinks are embedded. The thickness t1 of the chip and the thickness t2 of one of heat sinks that is joined to the chip using a solder satisfy the equation of t2/t1≧5. Furthermore, the thermal expansion coefficient &agr;1 of the heat sinks and the thermal expansion coefficient &agr;2 of the mold resin satisfy the equation of 0.5≦&agr;2/&agr;1≦1.5. In addition, the surface of the chip that faces the solder has a roughness Ra that satisfies the equation of Ra≦500 nm. Moreover, the solder is a Sn-based solder to suppress relaxation of a compressive stress in the chip, which is caused by the creeping of the solder.
    Type: Application
    Filed: July 24, 2002
    Publication date: January 30, 2003
    Inventors: Naohiko Hirano, Takanori Teshima, Yoshimi Nakase, Kenji Yagi, Yasushi Ookura, Kuniaki Mamitsu, Kazuhito Nomura, Yutaka Fukuda, Mikimasa Suzuki, Chikage Noritake
  • Patent number: 5656858
    Abstract: A semiconductor device, which has a high adhesiveness to the Cu film and the barrier metal at the bump part or LSI wiring part of a flip chip, is disclosed. On a silicon substrate are formed a transistor as a functional element and a bump for making contact with the transistor and an external substrate. On the surface of the silicon substrate is formed a metallic film, and on the metallic film is formed an insulating film, and a part of the metallic film is exposed through a contact hole. On the metallic film within the contact hole is formed a barrier metal made of TiN, and on the barrier metal is formed a bonding layer made of Ti. On the bonding layer is formed a bump growing Cu film, and on the bump growing Cu film is formed a bump structure.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: August 12, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Ichiharu Kondo, Chikage Noritake, Yusuke Watanabe