Abstract: A design method for a scan circuit includes reading timing constraint information, a net list and layout information, to extract a multicycle path route from routes existing in a semiconductor integrated circuit, dividing the multicycle path route extracted by a number of cycles, and adding a test circuit at each of locations divided by the number of cycles.

Abstract: According to one embodiment, a semiconductor integrated circuit includes memories, comparison circuits, first registers and a BIST. The comparison circuits compare output values of the memories with expected values, respectively. The first registers store comparison result data in the comparison circuits, respectively. The BIST controls tests of the memories and generates the expected values. A relief data generator generates relief data indicating the presence of a defect of each of the memories and a failure position on the basis of the comparison result data stored in a second register in the BIST. A third registers store the relief data and are smaller in number than the memories. A judgment circuit outputs a relief impossible signal when the total number of the relief data is greater the number of the third registers.

Abstract: According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal. When the memory is tested using a BIST circuit, the first selection unit selects a memory signal output from the memory in response to the test signal. When the BIST circuit is tested, the first selection unit selects the bypass signal. If the memory is tested, the compression unit holds a signal output from the first selection unit and if the BIST circuit is tested, the compression unit compresses and holds the signal output from the first selection unit. The comparison unit compares the signal held in the compression unit with an expectation value signal of the memory signal which is generated in the BIST circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit includes memories, comparison circuits, first registers and a BIST. The comparison circuits compare output values of the memories with expected values, respectively. The first registers store comparison result data in the comparison circuits, respectively. The BIST controls tests of the memories and generates the expected values. A relief data generator generates relief data indicating the presence of a defect of each of the memories and a failure position on the basis of the comparison result data stored in a second register in the BIST. A third registers store the relief data and are smaller in number than the memories. A judgment circuit outputs a relief impossible signal when the total number of the relief data is greater the number of the third registers.

Abstract: A semiconductor device of an embodiment is provided with a memory, a register configured to store a first data group including test data and read/write instruction data to the memory, a first inversion portion having an inverting function of a value of the test data outputted from the register, a second inversion portion having the inverting function of a value of the read/write instruction data outputted from the register, first and second input portions configured to input a data inversion instruction to the first and second inversion portions, and a data switching portion configured to switch between a test data group obtained by applying predetermined processing to the first data group outputted from the register through the first and second inversion portions and a second data group used for reading/writing of data held in the memory during a system operation as input data into the memory.

Abstract: A semiconductor device of an embodiment is provided with a memory, a register configured to store a first data group including test data and read/write instruction data to the memory, a first inversion portion having an inverting function of a value of the test data outputted from the register, a second inversion portion having the inverting function of a value of the read/write instruction data outputted from the register, first and second input portions configured to input a data inversion instruction to the first and second inversion portions, and a data switching portion configured to switch between a test data group obtained by applying predetermined processing to the first data group outputted from the register through the first and second inversion portions and a second data group used for reading/writing of data held in the memory during a system operation as input data into the memory.

Abstract: According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal. When the memory is tested using a BIST circuit, the first selection unit selects a memory signal output from the memory in response to the test signal. When the BIST circuit is tested, the first selection unit selects the bypass signal. If the memory is tested, the compression unit holds a signal output from the first selection unit and if the BIST circuit is tested, the compression unit compresses and holds the signal output from the first selection unit. The comparison unit compares the signal held in the compression unit with an expectation value signal of the memory signal which is generated in the BIST circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.

Abstract: The built-in self-test (BIST) circuit includes an address generating circuit. The BIST circuit includes a data generating circuit. The BIST circuit includes a chip enable signal generating circuit. The BIST circuit includes a control signal generating circuit. The memory block circuit includes the multiple memories. The memory block circuit includes an address converting circuit that generates, based on the address signal, an address input signal corresponding to the address of the memory to be tested out of the multiple memories, and generates a memory selection signal for selecting the memory to be tested from the multiple memories. The memory block circuit includes a memory output selecting circuit that selects and outputs data from the memory to be tested out of the multiple memories, based on the memory selection signal.

Abstract: The built-in self-test (BIST) circuit includes an address generating circuit. The BIST circuit includes a data generating circuit. The BIST circuit includes a chip enable signal generating circuit. The BIST circuit includes a control signal generating circuit. The memory block circuit includes the multiple memories. The memory block circuit includes an address converting circuit that generates, based on the address signal, an address input signal corresponding to the address of the memory to be tested out of the multiple memories, and generates a memory selection signal for selecting the memory to be tested from the multiple memories. The memory block circuit includes a memory output selecting circuit that selects and outputs data from the memory to be tested out of the multiple memories, based on the memory selection signal.

Abstract: According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.

Abstract: A semiconductor integrated circuit includes a memory containing multiple memory bits that store predetermined data placed in a first address direction and a second address direction. The semiconductor integrated circuit includes a BIST (Built-in Self-Test) circuit that diagnoses a failure of the memory. The BIST circuit includes a BIST control circuit that controls a BIST on the memory. The BIST circuit includes a failure information table storing: a failed bit-cell position that is an address of a bit cell identified in the first address direction as a failed bit cell by the BIST conducted in the first address direction; the number of bit cell failures at the failed bit-cell position; and a failure overflow flag indicating whether the number of failures exceeds a predetermined upper value or not. The BIST circuit includes a result analyzer that outputs a BIST result obtained by the BIST on the memory.

Abstract: A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.

Abstract: A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a memory designated by an address. A short defect between wirings connected to the memory is detected by comparing the one-hot data written in the memory with the one-hot data before being written.

Abstract: A semiconductor integrated circuit has a plurality of memory devices each comprising a memory cell array which includes a plurality of memory cells to store data, a spare part which includes a redundant cell to avoid a memory cell judged to be defective in the plurality of memory cells and conduct redundancy repair on data, and a switching circuit to avoid the defective memory cell and conduct switching to the redundant cell; and a repair code decoding circuit comprising a storage circuit which stores a repair code, a decoder which outputs a repair decoded signal obtained by decoding the repair code, wherein the switching circuit respectively in the memory devices avoids a memory cell corresponding to the repair decoded signal and conducts switching to the redundant cell of the memory devices in accordance with the repair decoded signal.

Abstract: An on-chip failure analysis circuit for analyzing a memory has a memory in which data is stored, a built-in self test unit which tests the memory, a failure detection unit which detects a failure of the output of the memory, a fail data storage unit in which fail data is stored, the fail data including a location of the failure, a failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure, the failure analysis unit writing fail data including the analysis result in the fail data storage unit, and an analysis result output unit which outputs the analysis result of the failure analysis unit.

Abstract: A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to write the data pattern in the memory cell, output expected value data, and decide whether to continue a test or suspend the test to output failure information to outside, based on a comparison result of the data pattern outputted from the memory cell and the expected value data and a comparison result of the data pattern and the failed data pattern.

Abstract: A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure detecting signal output unit that is configured to receive the compared result and output a failure detecting signal; and a BIST circuit including: a BIST control unit that is configured to output an instruction and output a BIST status; a shift controller that is configured to receive a first clock signal, the BIST status signal, and the failure detecting signal and output sift enable signal; a shift counter that counts the number of clock pulses on the first clock signal; a first storage register that is configured to receive the first clock signal and the shift enable signal, and a second storage register that is configured to receive a second clock signal.

Abstract: A semiconductor integrated circuit has a plurality of memory devices each comprising a memory cell array which includes a plurality of memory cells to store data, a spare part which includes a redundant cell to avoid a memory cell judged to be defective in the plurality of memory cells and conduct redundancy repair on data, and a switching circuit to avoid the defective memory cell and conduct switching to the redundant cell; and a repair code decoding circuit comprising a storage circuit which stores a repair code, a decoder which outputs a repair decoded signal obtained by decoding the repair code, wherein the switching circuit respectively in the memory devices avoids a memory cell corresponding to the repair decoded signal and conducts switching to the redundant cell of the memory devices in accordance with the repair decoded signal.

Abstract: A semiconductor integrated circuit has a data generation circuit configured to generate first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory, a failure data generation circuit configured to generate second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal, and a timing circuit configured to adjust timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory.