Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.

Abstract: A method for generating a test vector of a semiconductor integrated circuit including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.