Patents by Inventor Chikara Kondo

Chikara Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10373657
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Chiaki Dono
  • Publication number: 20190221283
    Abstract: With the use of nucleotide sequence data concerning transcription products, transcriptome analysis is performed with higher precision. Concerning a plurality of data sets including the objective variable data and the gene expression level data, a plurality of subdata sets are generated by randomly deleting the gene expression level data, and the method of regularization is applied to the plurality of subdata sets to calculate relevant estimation formulae and then generate the lists of genes included in the estimation formula.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 18, 2019
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, THE UNIVERSITY OF TOKYO, National Agriculture and Food Research Organization, RYUKOKU UNIVERSITY
    Inventors: Satoshi KONDO, Chikara OHTO, Madoka ABE, Naohiro AOKI, Akari FUKUDA, Tatsuro HIROSE, Atsushi NAGANO
  • Publication number: 20190214061
    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
  • Patent number: 10338997
    Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
  • Patent number: 10287604
    Abstract: A technique by which the production of plant biomass can be significantly increased is provided. A protein phosphatase 2C gene having 3 consensus sequences comprising the amino acid sequences shown in SEQ ID NOS: 1-3 from the N-terminal side in such order is over-expressed.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: May 14, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi Kondo, Chikara Ohto, Norihiro Mitsukawa, Nobuhiko Muramoto, Kenichi Ogawa, Hiroki Sugimoto, Tomoko Tanaka, Madoka Yonekura
  • Publication number: 20190122708
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20190115057
    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second dock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
  • Patent number: 10262704
    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
  • Publication number: 20190096469
    Abstract: One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventor: Chikara Kondo
  • Publication number: 20190079893
    Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines. Additional apparatus and methods are disclosed.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 14, 2019
    Inventors: Akinori Funahashi, Chikara Kondo
  • Publication number: 20190034370
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Inventors: Chikara Kondo, Akinori Funahashi
  • Patent number: 10185652
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Patent number: 10181347
    Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 15, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventors: Naohisa Nishioka, Chikara Kondo
  • Publication number: 20180374532
    Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Inventor: Chikara Kondo
  • Patent number: 10163469
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20180357156
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Patent number: 10147477
    Abstract: One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 4, 2018
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Chikara Kondo
  • Patent number: 10146719
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Akinori Funahashi
  • Publication number: 20180341575
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Publication number: 20180293128
    Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the fist external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
    Type: Application
    Filed: May 17, 2018
    Publication date: October 11, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo