Abstract: A memory device may be provided, including a first planar electrode, a second planar electrode, and a switching element arranged between the first planar electrode and the second planar electrode to where a first side of the switching element is arranged over the first planar electrode and where a second side of the switching element is arranged under the second planar electrode. The switching element is thicker at the first side than the second side, and the switching element is configured to provide a conductive filament formation region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a thin film resistor and methods of manufacture. A structure includes: a thin film resistor having an opening and being between an upper insulator material and a lower insulator material; and a contact extending through the opening in the thin film resistor and into the lower insulator material.

Abstract: According to various embodiments, a spin diode device may include a magnetic tunnel junction stack. The magnetic tunnel junction stack may include a lower magnetic layer, a tunnel barrier layer over the lower magnetic layer, and an upper magnetic layer over the tunnel barrier layer. The lower magnetic layer may include a lower magnetic film. The tunnel barrier layer comprising an insulating material. The upper magnetic layer may include an upper magnetic film. Each of the lower magnetic film and the upper magnetic film may have perpendicular magnetic anisotropy.

Abstract: According to various embodiments, a spin diode device may include a magnetic tunnel junction stack. The magnetic tunnel junction stack may include a lower magnetic layer, a tunnel barrier layer over the lower magnetic layer, and an upper magnetic layer over the tunnel barrier layer. The lower magnetic layer may include a lower magnetic film. The tunnel barrier layer comprising an insulating material. The upper magnetic layer may include an upper magnetic film. Each of the lower magnetic film and the upper magnetic film may have perpendicular magnetic anisotropy.

Abstract: According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.

Abstract: According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.

Abstract: In a non-limiting embodiment, a semiconductor device may include a magnetic tunnel junction (MTJ) stack. The MTJ stack may include a reference layer comprising a magnetic layer, a first tunneling barrier layer arranged over the reference layer, a free layer comprising a magnetic layer arranged over the first tunneling barrier layer, and a capping layer arranged over the reference layer, the first tunneling barrier layer and the free layer. The capping layer may be a non-magnetic layer. According to various non-limiting embodiments, the capping layer may include a rare earth element. According to various non-limiting embodiments, the MTJ stack may further include a second tunneling barrier layer arranged between the free layer and the capping layer. The capping layer may contact the second tunneling barrier layer.

Abstract: A memory device may be provided, including a first planar electrode, a second planar electrode, and a switching element arranged between the first planar electrode and the second planar electrode to where a first side of the switching element is arranged over the first planar electrode and where a second side of the switching element is arranged under the second planar electrode. The switching element is thicker at the first side than the second side, and the switching element is configured to provide a conductive filament formation region.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a contact overlying a substrate, and a bottom electrode overlying the contact. The bottom electrode is in electrical communication with the contact, and the bottom electrode has a bottom electrode upper surface with a bottom electrode upper surface area. A magnetic tunnel junction memory cell overlies the bottom electrode and is in electrical communication with the bottom electrode. The magnetic tunnel junction memory cell has an MTJ bottom surface with an MTJ bottom surface area that is greater than the bottom electrode surface area.

Abstract: The disclosure relates generally to resistive switching nonvolatile random access memory (ReRAM) devices, and more generally to structures and methods of fabricating multiple conductive elements in ReRAM devices. A resistive memory device is presented, the device comprising a first electrode having a first work function, and a second electrode having a second work function, the first work function being different from the second work function. A dielectric layer is disposed between the first and second electrodes. The device further comprises a set of nanocrystal structures distributed in the dielectric layer. A conductive layer is also disposed in the dielectric layer.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.

Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.

Abstract: A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits and/or memory cells are provided. An exemplary method for fabricating integrated circuit includes forming a bottom electrode and forming a fixed layer over the bottom electrode. The fixed layer includes a hard layer over a base layer that includes a seed layer. The seed layer has a thickness of less than about 100 A. Further, the seed layer includes chromium (Cr). The method further includes forming at least a first tunnel barrier layer over the hard layer, forming a storage layer over the first tunnel barrier layer, and forming a top electrode over the storage layer.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.

Abstract: A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.