Patents by Inventor Chim-Seng Seet
Chim-Seng Seet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150108654Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.Type: ApplicationFiled: October 22, 2013Publication date: April 23, 2015Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong RAO, Meng Meng Vanessa CHONG, Chim Seng SEET, Hendro MARIO, Aison JOHN GEORGE, Chor Shu CHENG
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Patent number: 8828858Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.Type: GrantFiled: January 19, 2012Date of Patent: September 9, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
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Publication number: 20140167121Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate. A gate having a gate electrode and sidewall spacers are formed adjacent to sidewalls of the gate. A height HG of the gate is lower than a height HS of the sidewall spacers. A metal or metal alloy layer is deposited over the spacers, gate and the substrate. The substrate is processed to form metal silicide contact at least over the gate electrode. A top surface of the metal silicide contact over the gate electrode is about coplanar with a top of the sidewall spacer, and the difference between the height of the gate and spacers prevent formation of metal silicide filaments on top of the sidewall spacers.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Kwee Liang YEO, Chim Seng SEET, Zheng ZOU, Alex SEE
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Publication number: 20140117545Abstract: A copper layer is formed without copper hillocks. Embodiments includes providing a copper layer above a substrate, planarizing the copper layer, performing hydrogen (H2) plasma treatment on the copper layer in a first chamber, and forming a barrier layer over the copper layer in a second chamber, different from the first chamber.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. LtdInventors: Huang LIU, Xuesong Rao, Zheng Zou, Alex See, Lup San Leong, Liang Li, Chim Seng Seet
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Publication number: 20130187202Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
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Patent number: 8492236Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.Type: GrantFiled: January 12, 2012Date of Patent: July 23, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
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Publication number: 20130181259Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
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Patent number: 8354347Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.Type: GrantFiled: December 11, 2007Date of Patent: January 15, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Chun Hui Low, Chim Seng Seet, Mei Sheng Zhou, Liang Choo Hsia
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Publication number: 20120273949Abstract: Semiconductor devices are formed with a Cu or Cu alloy interconnect encapsulated by a substantially uniform MnO or Al2O3 layer. Embodiments include forming an opening having side surfaces and a bottom surface in a dielectric layer, forming a barrier layer on the side surfaces and the bottom surface of the opening and on an upper surface of the dielectric layer, treating the barrier layer with an oxygen plasma to form dangling oxygen atoms on the barrier layer, depositing a seed layer on the barrier layer, and filling the opening with Cu or a Cu alloy.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Huang Liu, Chim Seng Seet, Alex Kai Hung See
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Patent number: 8102054Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: GrantFiled: August 23, 2010Date of Patent: January 24, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Bei Chao Zhang, Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang Ee, Bo Tao, Tong Qing Chen, Liang Choo Hsia
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Publication number: 20100314774Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: ApplicationFiled: August 23, 2010Publication date: December 16, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Bei Chao ZHANG, Chim Seng SEET, Juan Boon TAN, Fan ZHANG, Yong Chiang EE, Bo TAO, Tong Qing CHEN, Liang Choo HSIA
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Patent number: 7803704Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: GrantFiled: August 22, 2008Date of Patent: September 28, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Bei Chao Zhang, Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang Ee, Bo Tao, Tong Qing Chen, Liang Choo Hsia
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Patent number: 7790617Abstract: A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.Type: GrantFiled: November 12, 2005Date of Patent: September 7, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yeow Kheng Lim, Wei Lu, Liang Choo Hsia, Jyoti Gupta, Chim Seng Seet, Hao Zhang
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Publication number: 20100044869Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Bei Chao ZHANG, Chim Seng SEET, Juan Boon TAN, Fan ZHANG, Yong Chiang EE, Bo TAO, Tong Qing CHEN, Liang Choo HSIA
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Publication number: 20090146296Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.Type: ApplicationFiled: December 11, 2007Publication date: June 11, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Jianhui YE, Huang LIU, Alex KH SEE, Wei LU, Chun Hui LOW, Chim Seng SEET, Mei Sheng ZHOU, Liang Choo HSIA
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Patent number: 7294241Abstract: A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.Type: GrantFiled: January 3, 2003Date of Patent: November 13, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chim Seng Seet, Bei Chao Zhang, San Leong Liew, John Sudijono, Lai Lin Clare Yong
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Patent number: 7253097Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.Type: GrantFiled: June 30, 2005Date of Patent: August 7, 2007Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yeow Kheng Lim, Chim Seng Seet, Tae Jong Lee, Liang-Choo Hsia, Kin Leong Pey
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Publication number: 20070001303Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Yeow Kheng Lim, Chim Seng Seet, Tae Jong Lee, Liang-Choo Hsia, Kin Leong Pey
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Publication number: 20040131878Abstract: A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.Type: ApplicationFiled: January 3, 2003Publication date: July 8, 2004Inventors: Chim Seng Seet, Bei Chao Zhang, San Leong Liew, John Sudijono, Lai Lin Clare Yong
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Patent number: 6403478Abstract: A new method for preventing intermittent high Kelvin via resistance is achieved. This is accomplished by lowering the chamber pressure during warm-up, which prevents the wafer temperature from rising above about 380° C. The present invention uses a pressure of between 2 and 3 Torr during warm-up of the wafer prior to barrier metal deposition rather than 5 Torr, which is conventionally used. Using the conventional pressure of 5 Torr the wafer temperature overshoots to about 395° C. before settling to about 380° C. By reducing the pressure to between 2 and 3 Torr, the thermal conductivity between the wafer heater and the wafer is reduced and the overshoot reduced or eliminated. The lower temperature reduces the deposition rate by approximately 10 angstroms over a 15 second deposition, but this is compensated for by an increase in deposition time. However, because the reaction is carried out in the reaction-limited regime, the step coverage will increase when wafer temperature is reduced.Type: GrantFiled: August 31, 2000Date of Patent: June 11, 2002Assignee: Chartered Semiconductor Manufacturing CompanyInventors: Chim-Seng Seet, Chyi Shyuam Chern, Juan Boon Tan