Patents by Inventor Chin-an Cheng

Chin-an Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110100556
    Abstract: A plasma system with an injection device is provided. The plasma system comprises a plasma cavity and an injection device. The plasma cavity comprises a first electrode and a second for generating plasma. The injection device comprises a plasma injection tube and at least a reactant injection tube. The plasma injection tube is connected to the plasma cavity. The plasma injection tube comprises an inlet, an outlet and an outer sidewall. The plasma injection tube injects the plasma from the inlet and guides the plasma out through the outlet. The outer sidewall has a width decreasing from the inlet to the outlet. The reactant injection tube is disposed outside of the outer sidewall. The reactant injection tube injects a reactant to the outer sidewall so that the reactant flows along the outer sidewall toward the outlet and mixes with the plasma at the outlet.
    Type: Application
    Filed: December 24, 2009
    Publication date: May 5, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chi-Hung Liu, Chen-Der Tsai, Wen-Tung Hsu, Chun-Hsien Su, Wen-Chin Cheng, Liang-Yi Chen
  • Publication number: 20110089578
    Abstract: A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 21, 2011
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chin-Cheng Yang
  • Patent number: 7927960
    Abstract: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape. The trenches are overfilled with a first metal layer, the excess of which is removed so that the height of the metal is level with the height of the oxide. An overlay setting is then obtained between a photoresist mask and the filled trenches before depositing a second metal layer over the oxide and trenches. The second metal layer is coated with the photoresist according to the overlay setting.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: April 19, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chin Cheng Yang, Chih Hao Huang
  • Publication number: 20110086499
    Abstract: A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 14, 2011
    Inventors: Chin-Cheng Chien, Chan-Lon Yang, Chiu-Hsien Yeh
  • Patent number: 7924354
    Abstract: A pixel structure includes a bright region and a pale region, and the pale region includes a first capacitance coupling region and a second capacitance coupling region. The first capacitance coupling region includes a first coupling capacitor, the second capacitance coupling region includes a second coupling capacitor, and the first coupling capacitor and the second coupling capacitor are connected in parallel.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: April 12, 2011
    Assignee: AU Optronics Corp.
    Inventors: Ying-Chi Lu, Tsung-Chin Cheng, Chih-Jen Hu
  • Patent number: 7923175
    Abstract: A photomask structure is described, including a substrate having multiple half-tone phase shift patterns on a device region and multiple opaque patterns on a die seal ring region. By using the photomask, a side lobe effect does not occur to the photoresist layer corresponding to the die seal ring region in the exposure step.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: April 12, 2011
    Assignee: MACRONIX International Co. Ltd.
    Inventors: Chun-Chung Huang, Chin-Cheng Yang
  • Publication number: 20110074314
    Abstract: A method for controlling electrical power of light emission diodes (LED) is provided. The above method comprises steps of providing a supply voltage to the LED driver; providing a driving current to the LED by the LED driver; obtaining an operating voltage of the LED; and adjusting the supply voltage according to the operating voltage of the LED.
    Type: Application
    Filed: March 17, 2010
    Publication date: March 31, 2011
    Applicant: LUMENS DIGITAL OPTICS INC.
    Inventor: Wen-Chin Cheng
  • Publication number: 20110070702
    Abstract: A method for fabricating a semiconductor device is provided. A high dielectric constant (high-k) layer and a work function metal layer are formed in sequence on a substrate. A hard mask layer is formed on the work function metal layer, where the material of the hard mask layer is lanthanum oxide. The work function metal layer is patterned by using the hard mask layer as a mask. The hard mask layer is then removed. Afterwards, a gate structure is formed on the substrate.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 24, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Hsien Lin, Chiu-Hsien Yeh
  • Publication number: 20110065737
    Abstract: This invention relates to macrocyclic compounds of formula (I) shown in the specification. These compounds can be used to treat hepatitis C virus infection.
    Type: Application
    Filed: September 15, 2009
    Publication date: March 17, 2011
    Applicant: TaiGen Biotechnology Co., Ltd.
    Inventors: Chen-Fu Liu, Kuang-Yuan Lee, Pei-Chin Cheng, Yo-Chin Liu, Pin Lo, Kuo-Feng Tseng, Chih-Ming Chen, Chi-Hsin Richard King, Chu-Chung Lin
  • Patent number: 7901872
    Abstract: An exposure process is described, for defining in a photoresist layer a plurality of first patterns having a first pitch and a second pattern between them that is wider than one first pattern. A first exposure step is conducted to the photoresist layer with a first photomask that has a plurality of the first patterns without a second pattern between them, wherein the first patterns on the first photomask have the first pitch only. A second exposure step is conducted to the photoresist layer with a second photomask that has a third pattern narrower than the second pattern at a position corresponding to the second pattern. The exposure dose of the first or second exposure step alone is not sufficient to define any pattern in the photoresist layer.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: March 8, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Hao Huang, Chin-Cheng Yang
  • Patent number: 7880274
    Abstract: A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: February 1, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 7875520
    Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: January 25, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
  • Patent number: 7877511
    Abstract: Methods and apparatus provide an adaptive load balancer that presents a virtual data system to client computer systems. The virtual data system provides access to an aggregated set of data, such as files or web service objects, available from a plurality of server data systems respectively operating within a plurality of server computer systems. The adaptive load balancer receives a client data access transaction from a client computer system that specifies a data access operation to be performed relative to the virtual data system presented to the client computer system. The adaptive load balancer processes the client data access transaction in relation to metadata associated with the virtual data system to provide access to the file or service object within a server computer system, or to access the metadata.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: January 25, 2011
    Assignee: F5 Networks, Inc.
    Inventors: Michael A. Berger, Robert T. Curley, Daniel J. Dietterich, JC Ferguson, Michael J. Homberg, Benjamin E. McCann, Jonathan C. Nicklin, David Porter, Suchi Raman, Craig S. Rasmussen, Michael J. Soha, Thomas J. Teixeira, Bryan T. Whitmore, Leonard F. Wisniewski, Chin-Cheng Wu
  • Patent number: 7862986
    Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of forming a mask layer on the material layer. A multiple patterning process is performed on the mask layer for transferring at least a first pattern from a first photomask through a first photoresist and a second pattern from a second photomask from a second photoresist layer into the mask layer without performing any etching process. The mask layer exposes a portion of the material layer and the mask layer is patterned at the time that the first photoresist layer and the second photoresist layer are developed respectively. An etching process is performed to pattern the material layer by using the mask layer as an etching mask.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: January 4, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 7858529
    Abstract: The method of the present invention includes providing a semiconductor substrate with a recess; performing a pre-cleaning step on the semiconductor substrate; and performing a first reduction step, a lateral etching step and a second reduction step on the semiconductor substrate. The MOS structure includes a semiconductor substrate, a gate structure on the semiconductor substrate, a pair of recesses with beak sections extending to and under the gate structure, and a strain material filling the recess. The recess inside the semiconductor substrate processed by the method including the lateral etching step forms a beak section.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: December 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Publication number: 20100315362
    Abstract: A touch-sensing liquid crystal display (LCD) panel including an active device array substrate, an opposite substrate, and a liquid crystal layer disposed therebetween is provided. The active device array substrate includes a first substrate, a pixel array, a plurality of touch-sensing pads, and an electric field shielding layer. The pixel array is disposed on the first substrate and includes a plurality of sub-pixels arranged in an array, a plurality of scan lines, and a plurality of data lines. The touch-sensing pads are disposed on the first substrate. The electric field shielding layer is disposed on the pixel array and arranged between sub-pixels adjacent to each other, and the electric field shielding layer includes a pattern. The opposite substrate includes a common electrode and a plurality of touch-sensing protrusions disposed above the touch-sensing pads. Therefore, when the touch-sensing LCD panel is pressed, press mura is substantially eliminated.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 16, 2010
    Applicant: Au Optronics Corporation
    Inventors: Tsung-Chin Cheng, Hong-Ji Huang, Yue-Hung Wu, Zeng-De Chen, Seok-Lyul Lee
  • Patent number: 7852305
    Abstract: A flat panel display includes pixel electrodes, multiplexers and a gate driver. The gate driver has an amorphous silicon gate structure and includes a displacement temporary storage unit having a plurality of shift registers each with a power supply source and a clock terminal. One of a first voltage and a second voltage is selected and transmitted to the power supply source, and one of the first voltage and a clock signal is selected and transmitted to the clock terminal according to an off-controlling signal for causing the pixel electrodes connected to the shift registers to discharge.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: December 14, 2010
    Assignee: Chimei Innolux Corporation
    Inventor: Chin-Cheng Tsai
  • Publication number: 20100310342
    Abstract: A method and an apparatus for transferring a substrate are described. In the method, a substrate is provided on the surface of a first plate at a first position, the first plate is moved from the first position to a second position in an upper space of a second plate, the substrate is lifted away from the surface of the first plate, the first plate is moved away from the second position, and the substrate is put on the surface of the second plate from the upper space. The apparatus includes a first plate and a second plate each having a surface for carrying the substrate, wherein the first plate can be moved between the first position and the second position.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 9, 2010
    Applicant: MACRONIX International Co., Ltd.
    Inventor: CHIN-CHENG YANG
  • Publication number: 20100309151
    Abstract: A touch panel and methods for manufacturing the same is provided. The method for manufacturing a touch panel includes providing a substrate and forming a photospacer layer on the substrate. Subsequently, a single lithography process is performed to the photospacer layer to define a main spacer and a sensor spacer. After forming a conductive layer on the main spacers and sensor spacers, a part of the conductive layer is removed to expose a top part and a part of a upper side of the main spacer. Accordingly, the conductive layer on the top part of the main spacer can be completely removed. In addition, the aperture ratio loss due to over-etching the conductive layer on the color filter can be prevented by the conductive layer remained on a lower side of the main spacer.
    Type: Application
    Filed: December 3, 2009
    Publication date: December 9, 2010
    Applicant: AU OPTRONICS CORP.
    Inventors: Tsung-Chin Cheng, Zeng-De Chen, Seok-Lyul Lee
  • Patent number: 7849084
    Abstract: A method for dynamic event matching. A domain model for each domain is defined. Individual requirements and preferences of a user are modeled to create a personal model. Dynamic requirements of a specific domain for the user are modeled. A dynamic event is generated. The dynamic event is obtained using an information server for format transformation to create an event model. The personal model is matched with the event model using a content-based method according to the domain model and the dynamic event. The user is informed of the matching results. The matching results are adjusted according to user feedback.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: December 7, 2010
    Assignee: Institute for Information Industry
    Inventors: Tse-Ming Tsai, Chin-Cheng Wu, Chun-Chieh Liao