Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: A method for fabricating a fin field-effect transistor (FinFET) device includes forming a first dielectric layer over a substrate and then etching the first dielectric layer and the substrate to form a first fin and a second fin. A second dielectric layer is formed along sidewalls of the first fin and the second fin. A protection layer is deposited over the first fin and the second fin. A portion of the protection layer and the first dielectric layer on the second fin is removed and the second fin is then recessed to form a trench. A semiconductor material layer is epitaxially grown in the trench. The protection layer is removed to reveal the first fin and the second fin.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

Abstract: A method for fabricating a fin field-effect transistor (FinFET) device includes forming a first dielectric layer over a substrate and then etching the first dielectric layer and the substrate to form a first fin and a second fin. A second dielectric layer is formed along sidewalls of the first fin and the second fin. A protection layer is deposited over the first fin and the second fin. A portion of the protection layer and the first dielectric layer on the second fin is removed and the second fin is then recessed to form a trench. A semiconductor material layer is epitaxially grown in the trench. The protection layer is removed to reveal the first fin and the second fin.

Abstract: A device includes a first fin including a first semiconductor material. A first dielectric layer is disposed over a top surface of the first fin. A sidewall of the first dielectric layer has a dip-shape profile. A second dielectric layer is disposed along sidewalls of the first fin. A top surface of the second dielectric layer is substantially coplanar with the top surface of the first fin. A second fin includes a second semiconductor material different from the first semiconductor material. An isolation region is disposed between the first fin and the second fin.

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract: A gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided. The VGAA device structure includes a substrate and an isolation structure formed in the substrate. The VGAA device structure also includes a first transistor structure formed on the substrate, and the first transistor structure includes a vertical structure. The vertical structure includes a source region, a channel region and a drain region, and the channel region is formed between the source region and the drain region. The channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure. The VGAA device structure further includes a gate stack structure wrapping around the channel region.

Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

Abstract: A semiconductor device includes a first transistor and a second transistor. Each of the first and second transistors includes a channel. The channel of the first transistor extends in a substantially vertical direction. The channel of the second transistor extends in a substantially horizontal direction. A method for fabricating the semiconductor device is also disclosed.

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract: A device includes a first fin including a first semiconductor material. A first dielectric layer is disposed over a top surface of the first fin. A sidewall of the first dielectric layer has a dip-shape profile. A second dielectric layer is disposed along sidewalls of the first fin. A top surface of the second dielectric layer is substantially coplanar with the top surface of the first fin. A second fin includes a second semiconductor material different from the first semiconductor material. An isolation region is disposed between the first fin and the second fin.

Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.