Abstract: An active device array substrate at least including a substrate, a plurality of pixel units, a plurality of first signal lines, a first connecting wire, a plurality of first switching devices, and a plurality of second signal lines is provided. The pixel units are disposed within an active area. One ends of two neighboring first signal lines are respectively connected to a first test line and a second test line. The other ends of the two neighboring first signal lines are both connected to the first switching devices. Moreover, the first connecting wire is electrically connected to the first switching devices. One ends of two neighboring second signal lines are respectively connected to a third test line and a fourth test line.

Abstract: A display panel have a transmissive region and a reflective region. The display panel comprises a first plate, a second plate opposite to the first plate and a display medium. The first plate comprises a first substrate, a scan line, a data line, an active device, a common electrode, a pixel electrode and a dielectric layer. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device and is electrically insulated from the common electrode. The pixel electrode has slits exposing the common electrode. The dielectric layer is located between the common electrode and the pixel electrode and has first openings in the reflective region. The second plate is opposite to the first plate. The display medium is located between the first plate and the second plate.

Abstract: The present invention discloses a pixel with pre-charge function. Being added into every pixel of a TFT-LCD, a pre-charging transistor can charge the capacitor of a pixel to a pre-designed voltage in advance before the pixel updates its gray level. Owing to the reduced charging voltage, the charging and discharging time is reduced thereof when the pixel updates its grey level. Furthermore, the problems of low contrast ratio and flicker, due to insufficient charging or discharging time, are solved.

Abstract: A liquid crystal display panel for solving color shift includes a first pixel, a second pixel and a third pixel. The first pixel includes a first pixel electrode and a first storage electrode having a first common voltage. The first pixel electrode and the first storage electrode form a first storage capacitor. The second pixel includes a second pixel electrode and a second storage electrode having a second common voltage. The second pixel electrode and the second storage electrode form a second storage capacitor. The third pixel includes a third pixel electrode and a third storage electrode having a third common voltage. The third pixel electrode and the third storage electrode form a third storage capacitor. The first common voltage is not equal to at least one of the second common voltage and the third common voltage.

Abstract: An electrostatic discharge (ESD) protection circuit electrically connected to a first conductive line and a second conductive line is provided. The ESD protection circuit has a first ESD protection circuit unit, wherein the first ESD circuit unit includes a first coupled capacitor and a first active device. The first coupled capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conductive line. The first active device includes a first gate, a first source and a first drain, wherein the first gate is electrically connected to the second electrode. In addition, the first source and the first electrode are electrically connected to the first conductive line, and the first drain is electrically connected to the second conductive line. Therefore, the conduction efficiency of the ESD protection circuit is improved.

Abstract: A liquid crystal display panel includes a plurality of scan lines and a plurality of pixels. Each scan line has a signal-input end, and each pixel includes a gate electrode, a drain electrode, an extending electrode and a coupling capacitor. The extending electrode is an extending part of the drain electrode, and does not overlap the gate electrode. Each coupling capacitor is coupled between each extending electrode and the corresponding scan line. In each scan line, capacitances of the coupling capacitors between the extending electrodes and the corresponding scan line increase as distances between the extending electrodes and the corresponding signal-input end increase.

Abstract: A transistor array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units. The scan lines, the data lines, and the pixel units are all disposed on the substrate. Each pixel unit includes a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, a first storage capacitor, and a second storage capacitor. The second transistor and the first transistor are electrically connected with the same scan line and the same data line. The second transistor and the first transistor are connected in series. The first pixel electrode is electrically connected with the first transistor, and the second pixel electrode is electrically connected with the second transistor. The first storage capacitor is electrically connected with the first transistor and the second transistor, and the second storage capacitor is electrically connected with the second transistor.

Abstract: A pixel structure adapts for compensating variation of gate-drain parasitic capacitance caused by misalignment in manufacturing process by forming a transverse compensation capacitance between a capacitance compensation portion and a scan line in an in-plane direction, and therefore the flicker in displaying of a display panel can be alleviated. In addition, being applied into a concept of “data lines reducing”, the pixel structure is capable of reducing difference of capacitance between two adjacent pixel structures due to misalignment in manufacturing process and improving display uniformity. Furthermore, a thin film transistor array substrate, a display panel, and a display apparatus applying the pixel structure are also provided.

Abstract: An active device array substrate including a substrate, an active device array, an detecting circuit, a plurality of driver chip pads, a plurality of flexible printed circuit (FPC) pads, a plurality of connection lines and an inner shorting ring is provided. The active device array and the detecting circuit are disposed on the substrate, and the detecting circuit is electrically connected to the active device array. The driver chip pads and the FPC pads are disposed on the substrate, wherein the driver chip pads are electrically connected to the active device array. The connection lines are disposed on the substrate, and each of the connection lines is respectively connected to the detecting circuit and the corresponding FPC pad. The inner shorting ring is disposed on the substrate, and the inner shorter ring is respectively electrically connected to the corresponding FPC pad and the active device array.

Abstract: The present invention provides driving circuit for a liquid crystal display with data line reducing abilities. A first sub scan signal line and a second sub scan signal line of a first main sub scan signal line disposed outside of an active area are connected to a first control transistor and a second control transistor. A gate of the first control transistor disposed outside of the active area is connected to a first sub scan signal line of next main scan signal line of the first main scan signal line. A gate of the second control transistor disposed outside of the active area is connected to a first sub scan signal line of next main scan signal line of the next main scan signal line.

Abstract: A liquid crystal display panel includes a plurality of scan lines and a plurality of pixels. Each scan line has a signal-input end, and each pixel includes a gate electrode, a drain electrode, an extending electrode and a coupling capacitor. The extending electrode is an extending part of the drain electrode, and does not overlap the gate electrode. Each coupling capacitor is coupled between each extending electrode and the corresponding scan line. In each scan line, capacitances of the coupling capacitors between the extending electrodes and the corresponding scan line increase as distances between the extending electrodes and the corresponding signal-input end increase.

Abstract: A pixel structure adapts for compensating variation of gate-drain parasitic capacitance caused by misalignment in manufacturing process by forming a transverse compensation capacitance between a capacitance compensation portion and a scan line in an in-plane direction, and therefore the flicker in displaying of a display panel can be alleviated. In addition, being applied into a concept of “data lines reducing”, the pixel structure is capable of reducing difference of capacitance between two adjacent pixel structures due to misalignment in manufacturing process and improving display uniformity. Furthermore, a thin film transistor array substrate, a display panel, and a display apparatus applying the pixel structure are also provided.

Abstract: An active device array substrate at least including a substrate, a plurality of pixel units, a plurality of first signal lines, a first connecting wire, a plurality of first switching devices, and a plurality of second signal lines is provided. The pixel units are disposed within an active area. One ends of two neighbouring first signal lines are respectively connected to a first test line and a second test line. The other ends of the two neighbouring first signal lines are both connected to the first switching devices. Moreover, the first connecting wire is electrically connected to the first switching devices. One ends of two neighbouring second signal lines are respectively connected to a third test line and a fourth test line.

Abstract: An electrostatic discharge (ESD) protection circuit electrically connected to a first conductive line and a second conductive line is provided. The ESD protection circuit has a first ESD protection circuit unit, wherein the first ESD circuit unit includes a first coupled capacitor and a first active device. The first coupled capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conductive line. The first active device includes a first gate, a first source and a first drain, wherein the first gate is electrically connected to the second electrode. In addition, the first source and the first electrode are electrically connected to the first conductive line, and the first drain is electrically connected to the second conductive line. Therefore, the conduction efficiency of the ESD protection circuit is improved.

Abstract: An active device array substrate including a substrate, an active device array, an detecting circuit, a plurality of driver chip pads, a plurality of flexible printed circuit (FPC) pads, a plurality of connection lines and an inner shorting ring is provided. The active device array and the detecting circuit are disposed on the substrate, and the detecting circuit is electrically connected to the active device array. The driver chip pads and the FPC pads are disposed on the substrate, wherein the driver chip pads are electrically connected to the active device array. The connection lines are disposed on the substrate, and each of the connection lines is respectively connected to the detecting circuit and the corresponding FPC pad. The inner shorting ring is disposed on the substrate, and the inner shorter ring is respectively electrically connected to the corresponding FPC pad and the active device array.

Abstract: An active device array mother substrate suitable for being divided into a plurality of active device array substrates is provided. The active device array mother substrate includes a substrate, multiple sets of active device arrays, and a plurality of outer circuit pads. The substrate has a plurality of predetermined regions defining the positions of the active device array substrates respectively. Furthermore, the multiple sets of active device arrays are disposed in the predetermined regions respectively and the pads are also disposed in the predetermined regions. The pads and the active device arrays in the predetermined regions are electrically connected to each other. Particularly, the pads of at least two predetermined regions are electrically connected to each other.

Abstract: Pixel units are disposed in a display region of a substrate, and scan lines and data lines are used to control the pixel units. Inner short ring includes a first segment, a second segment and a connecting segment connecting both segments. The gates and sources of the first and second active device connect with the first and second segments respectively, and the drains connect with the connecting segment. The gates and sources of part of the third active devices connect with the first segment, and the drains connect with the odd scan lines. The gates and sources of other third active devices connect with the second segment, and the drains connect with the even scan lines. The gates of the fourth active devices connect with connecting lines, and the sources connect with data testing lines, and the drains connect with the odd and even data lines respectively.

Abstract: Pixel units are disposed in a display region of a substrate, and scan lines and data lines are used to control the pixel units. Inner short ring includes a first segment, a second segment and a connecting segment connecting both segments. The gates and sources of the first and second active device connect with the first and second segments respectively, and the drains connect with the connecting segment. The gates and sources of part of the third active devices connect with the first segment, and the drains connect with the odd scan lines. The gates and sources of other third active devices connect with the second segment, and the drains connect with the even scan lines. The gates of the fourth active devices connect with connecting lines, and the sources connect with data testing lines, and the drains connect with the odd and even data lines respectively.

Abstract: An electrostatic discharge protection structure contains a short ring surrounding a display region comprising pixel electrodes and thin film transistors, a plurality of switching elements disposed between the display region and the short ring corresponding to the scan lines and data lines, at least one of which is turned on to electrically connect the short ring and the scan lines and the data lines for introducing electrostatic charges to the short ring when a specific amount of electrostatic charges accumulate on the scan lines and the data lines, a conducting wire electrically connecting a storage capacitor line and the short ring, and a floating conductive pattern crossing over and not contacting the conducting wire, thereby assisting the electrostatic charges in distributing in the floating conductive pattern. Thus, an electrostatic discharge protection can be performed efficiently without increasing the substrate size.