Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Abstract: The present invention provides a method of culturing microorganisms normally grown on a solid in liquid media, methods of use thereof to determine the presence or absence of the microorganism in a sample, and methods of use in a mutation accumulation assay.

Abstract: The disclosure provides compounds that inhibit the invasion of host cells by intracellular pathogens. The disclosure also relates to use of such compounds in methods of treating and preventing periodontitis or a periodontitis-related condition or symptom.

Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: Disclosed herein are related to a method of amplifying an input voltage based on cascaded charge pump boosting. The method includes storing, by a first capacitor, first electrical charges corresponding to an input voltage to obtain a second voltage. The method further includes amplifying, by a voltage amplifier, the second voltage according to the first electrical charges stored by the first capacitor to obtain a third voltage. The method further includes storing, by a second capacitor, second electrical charges according to the third voltage. The method further includes amplifying, by the voltage amplifier, the third voltage according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.

Abstract: The disclosure provides compounds that inhibit the invasion of host cells by intracellular parasites. These find use, for example, in treating and preventing periodontitis or a periodontitis-related condition or symptom.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: A method of amplifying an input voltage based on cascaded charge pump includes generating, at a set of capacitors, an input voltage corresponding to input data. The method further includes storing, by a first capacitor, first electrical charges corresponding to the input voltage to obtain a second voltage. The method further includes amplifying, a voltage amplifier, the second voltage according to the first electrical charges stored by the first capacitor to obtain a third voltage. The method further includes storing, by a second capacitor, second electrical charges according to the third voltage. The method further includes amplifying, by the voltage amplifier, the third voltage according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: The present invention provides a use of platelet dry powder (PDP) for relieving inflammation or injury in an airway portion, wherein per gram of platelet dry powder (PDP) comprises at least 100,000 platelets.

Abstract: The disclosure provides compounds that inhibit the invasion of host cells by intracellular parasites. These find use, for example, in treating and preventing periodontitis or a periodontitis-related condition or symptom.

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Abstract: The present disclosure provides a platelets-containing composition and the preparation process thereof. The platelets-containing composition includes a quantified and activated platelet-rich plasma and a platelet-poor plasma mixed with the quantified and activated platelet-rich plasma. The preparation process of the platelets-containing composition is to purify and quantify platelets from the collected whole blood to produce the platelets-containing composition with high purity, which can have the best growth factor sustained-release effect.

Abstract: A carrier for solid state devices includes a plurality of panels, at least one gate, and an addition. The plurality of panels includes a first panel, a second panel, and a third panel. The at least one gate is attached to the second panel and the third panel. The at least one gate is configured to be in one of a first position or a second position. When the at least one gate is in the first position, an opening for receiving solid state devices is at least partially occluded to a first width that is smaller than a length of one of the solid state devices. When the at least one gate is in the second position, the opening for receiving the solid state devices is increased to a second width that is larger than the length of the one of the solid state devices.