Abstract: A power supply system includes a housing having a top cover with a cutout portion formed near a rear end thereof. The cutout portion is configured to mechanically receive, one at a time, either a first bracket or a second bracket to be coupled to the top cover. The first bracket is configured to accommodate a first power supply component. The second bracket is configured to accommodate a second power supply component of a different type than the first power supply component. Each of the first bracket and the second bracket has a length and/or a width greater than a length and a width, respectively, of the cutout portion. Each of the first power supply component and the second power supply component is either a conventional power supply unit, or a busbar adapter sled configured to electrically connect with a busbar cable that supplies power from a remote power source.

Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.

Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.

Abstract: A power supply system includes a housing having a top cover with a cutout portion formed near a rear end thereof. The cutout portion is configured to mechanically receive, one at a time, either a first bracket or a second bracket to be coupled to the top cover. The first bracket is configured to accommodate a first power supply component. The second bracket is configured to accommodate a second power supply component of a different type than the first power supply component. Each of the first bracket and the second bracket has a length and/or a width greater than a length and a width, respectively, of the cutout portion. Each of the first power supply component and the second power supply component is either a conventional power supply unit, or a busbar adapter sled configured to electrically connect with a busbar cable that supplies power from a remote power source.

Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Abstract: A fleet vehicle management system includes an edge device disposed in a vehicle and a cloud device. A processing module of the edge device acquires around-view image and determines at least one traffic indication accordingly. The nearing event warning module of the edge device sends out a nearing event alert to a driver via an output module. The after event detection module of the edge device acquires GPS informations in a first time interval and a second time interval respectively to determine whether the vehicle meets an after event criterion. A violation event is triggered if the after event criterion is met. A database of the cloud device stores the nearing event alert, a driving violation result and a driving record information. The driver behavior analysis module generates an information for evaluating a driving score based on the nearing event, the violation event and the driving record information.

Abstract: The present invention provides an automatic system for visual guidance and navigation using real-time visual anchor point detection, which includes an edge device, a cloud device, and a landmark database; the system of the present invention provides users with navigation directions via visual landmarks. A candidate visual landmark image is selected from the database; the system of the present invention can calculate the time of day, the current weather condition, the current season, etc. In addition, the system of the present invention can use the camera on the dashboard of the vehicle, the camera in the smartphone, or other cameras to collect real-time images; the system of the present invention can also provide feedback on the visibility or salience of landmarks to improve the visual landmark images obtained by subsequent users.

Abstract: A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a first gate structure, and a second gate structure. The substrate includes at least one first trench group and at least one second trench group spaced apart from each other. The first trench group includes first trenches spaced apart from each other in a first direction and extending in a second direction other than the first direction. The second trench group includes second trenches spaced apart from each other in the second direction and extending in the first direction. The first gate structure is disposed in each of the first trenches and extends in the second direction. The second gate structure is disposed in each of the second trenches and extends in the first direction.

Abstract: A sensor device adapted to suit curved surfaces includes a flexible substrate, a plurality of sensing units and a plurality of connecting lines. The flexible substrate includes a plurality of connecting sections, wherein each of the plurality of connecting sections comprises at least one closed hollow region. A plurality of sensing units, disposed on the flexible substrate and arranged in an array; and a plurality of connecting lines, disposed on the flexible substrate. Each of the plurality of connecting lines is connected to two adjacent ones of the plurality of sensing units, and the plurality of connecting sections are respectively overlapped with the plurality of connecting lines.

Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: The present invention provides a use of platelet dry powder (PDP) for relieving inflammation or injury in an airway portion, wherein per gram of platelet dry powder (PDP) comprises at least 100,000 platelets.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: The present invention discloses a system and a method of walkie-talkie communication crossing various wireless frequency domains. The system includes walkie-talkies, communication servers, and a connection network connecting the communication servers for mutual communication. The walkie-talkies are divided into communication groups, and each communication group is assigned to one specific communication server. The walkie-talkies and the communication server in the same communication group employ an exclusive wireless channel to wirelessly communicate. In particular, the communication server is invoked by one of the walkie-talkies in the same communication group to perform a broadcasting process for the walkie-talkies in different communication groups to broadcast at the same time. The present invention is suitably applied to any indoor or outdoor environments as long as the communication servers are provided.

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: A hot swap battery module uses a smart chip and an ideal diode controller to control a power transistor so as to implement a multi-step charge or discharge. Consequently, battery modules which have different voltages or battery capacities can be immediately connected in parallel. When the hot swap battery module is hot swapped, the hot swap battery module also can avoid an excessive charge current or discharge current to damage itself.