Patents by Inventor Chin Hsi Lin
Chin Hsi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7085160Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.Type: GrantFiled: October 6, 2004Date of Patent: August 1, 2006Assignees: Kabushiki Kaisha Toshiba, Solid State System Co., Ltd.Inventors: Hitoshi Shiga, Chin Hsi Lin
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Patent number: 7061042Abstract: A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.Type: GrantFiled: June 18, 2004Date of Patent: June 13, 2006Assignee: Solid State System Co., Ltd.Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Patent number: 7046549Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.Type: GrantFiled: December 31, 2003Date of Patent: May 16, 2006Assignee: Solid State System Co., Ltd.Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20060086967Abstract: A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.Type: ApplicationFiled: December 7, 2005Publication date: April 27, 2006Inventors: Tsung-Min Hsieh, Jhyy-Cheng Liou, Chien-Hsing Lee, Chin-Hsi Lin
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Publication number: 20060067118Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.Type: ApplicationFiled: September 21, 2005Publication date: March 30, 2006Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20060067124Abstract: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.Type: ApplicationFiled: September 21, 2005Publication date: March 30, 2006Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Patent number: 7020018Abstract: A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.Type: GrantFiled: November 12, 2004Date of Patent: March 28, 2006Assignee: Solid State System Co., Ltd.Inventors: Tsung-Min Hsieh, Jhyy-Cheng Liou, Chien-Hsing Lee, Chin-Hsi Lin
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Patent number: 7015553Abstract: A compact mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines, a plurality of bit lines, and a plurality of MOS-type and diffusion-type memory cells arranged in an array. The memory cells in one column are coupled to one bit line, and the gates of the MOS-type cells in one row are coupled to one word line via contacts, wherein two columns of memory cells share a column of contacts. A MOS-type cell shares its source and drain with two memory cells in the same column, and a diffusion-type cell directly connects with the diffusions of two adjacent memory cells. A constant number of continuous memory cells are grouped as a memory string, wherein the two diffusions of the two terminal memory cells are electrically connected to a bank select transistor and a ground line, respectively.Type: GrantFiled: August 26, 2002Date of Patent: March 21, 2006Assignee: Solid State System Co., Ltd.Inventors: Jhyy-Cheng Liou, Chin-Hsi Lin
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Publication number: 20060056226Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.Type: ApplicationFiled: November 9, 2005Publication date: March 16, 2006Inventors: Chin-Hsi Lin, Chi-Ming Weng
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Publication number: 20060013041Abstract: The invention is directed to a via-mask read only memory (ROM) layout structure, including a dynamic random access memory (DRAM) like layout structure, serving as a main body structure and having an array of coding transistors. A grounding structure line is disposed over the source regions of the coding transistors. The grounding layer is located at a position, where capacitor areas are defined in a DRAM structure. A plurality of vias are corresponding to a portion of the coding transistors, for coupling the source regions with the grounding structure line. Each of the vias in the corresponding coding transistors represents a first binary data, and the coding transistors without the vias represent a second binary data.Type: ApplicationFiled: September 23, 2005Publication date: January 19, 2006Inventor: Chin-Hsi Lin
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Patent number: 6987298Abstract: A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.Type: GrantFiled: April 12, 2004Date of Patent: January 17, 2006Assignee: Solide State System Co., Ltd.Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20060007724Abstract: A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.Type: ApplicationFiled: September 7, 2005Publication date: January 12, 2006Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20060002169Abstract: A FeRAM array configured in a ROM format is provided. The FeRAM array includes a memory array that has a plurality of segmented BL/PL arrays, and each segmented BL/PL array defines an I/O. A plurality of charge transfer sense amplifiers is further provided. Each charge transfer sense amplifier is associated with each I/O, and each charge transfer sense amplifier includes a cross coupled latch that is connected between a memory cell access portion and a reference voltage generation portion of the charge transfer sense amplifier. The reference voltage generation portion further includes a reference bitline (Crb) coupled to a reference voltage (Vr), and the reference bitline (Crb) is coupled to a pair of dummy capacitance cells. Each of the dummy capacitance cells is preset before reading at an opposite relative polarity.Type: ApplicationFiled: July 2, 2004Publication date: January 5, 2006Inventor: Chin-Hsi Lin
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Publication number: 20050265077Abstract: A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.Type: ApplicationFiled: August 2, 2005Publication date: December 1, 2005Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20050237777Abstract: A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.Type: ApplicationFiled: November 12, 2004Publication date: October 27, 2005Inventors: Tsung-Min Hsieh, Jhyy-Cheng Liou, Chien-Hsing Lee, Chin-Hsi Lin
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Publication number: 20050224865Abstract: A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.Type: ApplicationFiled: April 12, 2004Publication date: October 13, 2005Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20050170588Abstract: The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing the data storage capacity.Type: ApplicationFiled: July 7, 2004Publication date: August 4, 2005Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20050167731Abstract: A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.Type: ApplicationFiled: June 18, 2004Publication date: August 4, 2005Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20050170589Abstract: The present invention relates to a fabrication method for a mask read only memory structure. By forming double spacers, the code implantation can be performed in a self-aligned way into the channel regions of predetermined memory cells. By avoiding erroneous implantation to the non-channel regions and thus the laterally diffusion of the un-wanted impurities to the channel regions of non-coded memory cells, the threshold voltage of the non-coded memory cells can be unaffected and the error rate of reading can be greatly reduced.Type: ApplicationFiled: July 7, 2004Publication date: August 4, 2005Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou
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Publication number: 20050167730Abstract: The invention is directed to a nonvolatile memory device. Each memory cell is formed to have the depletion mode operation by doped opposite conductive-type dopants to the substrate at the surface region under the gate electrode, so that the depletion memory cell is formed. The charge-storing structure layer is, for example, an O/N/O structure layer, wherein the nitride layer is used to store the charge. The erasing operation speed can be improved.Type: ApplicationFiled: May 17, 2004Publication date: August 4, 2005Inventors: Chien-Hsing Lee, Chin-Hsi Lin, Jhyy-Cheng Liou