Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer.

Abstract: A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located between the first package and the second package, where the at least one gap controller is configured to provide a minimum gap between the first package and the second package. The first package includes a first electronic package component (e.g., first die). In some implementations, the at least one gap controller is coupled to the first package, but free of coupling with the second package. The at least one gap controller is located on or about a center of the first package. The at least one gap controller may be located between the first electronic package component (e.g., first die) and the second package. The package on package (PoP) device may include an encapsulation layer between the first package and the second package.

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

Abstract: Conventional ways of coupling die packages to external devices include providing contacts on a separate area on a printed circuit board (PCB). These PCB contacts are configured to mate with connector contacts of a connector to enable coupling with external devices. Unfortunately, the PCB contacts take up significant amount of area of the PCB. Also, the connection can suffer from parasitic losses and signal integrity can be compromised. An on-package connection is proposed to address the short comings of the conventional ways. The on-package connection enables a die package to connect directly with the connector. This removes the need to provide a separate area for PCB contacts. Also, parasitic losses are minimized and signal integrity is enhanced.

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

Abstract: To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

Abstract: A semiconductor package for a side by side die configuration may include a substrate having a cavity, a bridge interposer positioned within the cavity and having an active side facing active sides of a first die and a second die and partially horizontally overlapping the first die and the second die to provide an interconnection between the first die and the second die, and a thermal element attached to backsides of the first die and the second die to provide a heat path and heat storage for the first die and the second die.

Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (?m) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract: Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material.

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract: A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.

Abstract: Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (?m) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC.