Abstract: This present invention provides a method for continuously maintaining growth of a motor neuron progenitor cell and a pharmaceutical composition. Wherein, the method for continuously maintaining growth of a motor neuron progenitor cell is to culture the motor neuron progenitor cell in an environment which is constructed by the olfactory ensheathing cells to make the motor neuron progenitor cell sustain the ability to self-replicate and to be induced for differentiating into mature neuron, and therefore to elaborate the effect to protect the motor neuron. The motor neuron progenitor cell produced from the method disclosed in this present invention can be an effective ingredient of the pharmaceutical composition for treating related diseases of damaged motor neuron.

Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

Abstract: The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Abstract: An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.

Abstract: A method for decoding a bitstream by an apparatus, includes obtaining a decoded audio signal and metadata from the bitstream, the metadata comprising scene orientation information; and rendering the decoded audio signal based on the scene orientation information, wherein the scene orientation information is information for a direction of a video scene related to the decoded audio signal.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: An optical detecting device capable of detecting a lift height of an optical navigation apparatus is disclosed. The optical detecting device includes a sensor module and a processor. The sensor module includes a sensor array and at least one detector strip. The sensor array is adapted to acquire navigation information of the optical navigation apparatus moved relative to a working surface by sensing an illumination area, and the detector strip has a detection region across an edge of the illumination area. The processor is electrically connected to the sensor module, and adapted to compute the lift height of the optical navigation apparatus relative to the working surface according to a detection result of the detector strip.

Abstract: A motor controller comprises a driving circuit, a selection circuit, a sensorless control circuit, a Hall signal control circuit, a detection circuit, a first input terminal, and a second input terminal. The Hall signal control circuit may be coupled to a Hall sensor via the first input terminal and the second input terminal. When each of the voltage of the first input terminal and the voltage of the second input terminal is at a low level, the motor controller is operated in a sensorless driving mode. When one of the voltage of the first input terminal and the voltage of the second input terminal is at a high level, the motor controller is operated in a Hall control driving mode.

Abstract: A motor controller is configured to stabilize a motor current. The motor controller is used for driving a motor, where the motor has a motor coil. The motor controller comprises a switch circuit, a control unit, a command unit, a counting unit, a comparing unit, and a phase detecting unit. The switch circuit is used for supplying the motor current to the motor coil. The phase detecting unit generates a phase signal to the control unit, so as to inform the control unit to switch phases. The control unit generates a plurality of control signals to control the switch circuit. The motor controller resets the counting unit based on the phase signal, such that the control signals are synchronized with the phase signal for stabilizing the motor current.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.

Abstract: A motor controller is configured to stabilize a motor current. The motor controller is used for driving a motor, where the motor has a motor coil. The motor controller comprises a switch circuit, a control unit, a command unit, a counting unit, a comparing unit, and a phase detecting unit. The switch circuit is used for supplying the motor current to the motor coil. The phase detecting unit generates a phase signal to the control unit, so as to inform the control unit to switch phases. The control unit generates a plurality of control signals to control the switch circuit. The motor controller resets the counting unit based on the phase signal, such that the control signals are synchronized with the phase signal for stabilizing the motor current.

Abstract: The present invention is related to a thin heat dissipation device and a method for manufacturing the same. The device of the present invention mainly comprises a hollow body having an enclosed chamber and a working fluid with which the enclosed chamber is filled. The enclosed chamber comprises a first fluid channel and a second fluid channel. The first and second fluid channels extend in the longitudinal direction of the hollow body, are juxtaposed in the width direction of the hollow body and communicated with each other, and an interface between the first fluid channel and the second fluid channel has a height of about 0.1 mm or less. As such, a novel capillary structure which is capable of greatly reducing the entire thickness, enhancing heat transfer efficiency and reducing cost and which is reliable and durable is provided.