Abstract: The present random access PCR reactor for biological analysis, comprises of a number of PCR reactors held on a platform, and one optical system to be shared by all of the PCR reactors on the platform. The optical system is held on a traverse mechanism to move it over any one of the PCR reactors that are ready to be imaged. Other PCR reactors on the platform can be accesses and replaced. The optical system has a lightpipe and a lightguide that distributes a uniform light over all the samples held on the reactor. The lightguide of the present optical system has a set of light reflecting structures that are strategically located to uniformly reflect an incoming light towards all the samples held in the PCR reactor that is being tested.

Abstract: A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

Abstract: An interconnection structure is provided. The interconnection structure includes an etching-process-free first dielectric layer, a first conductive structure extending within the first dielectric layer, a second dielectric layer formed under the first dielectric layer, and a second conductive structure extending through both the first dielectric layer and the second conductive layer.

Abstract: Provided are a polyimide-based film, a window cover film, and a display panel including the same. More particularly, a polyimide-based film having different surface properties of both surfaces is provided.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adj acent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

Abstract: Disclosed herein are methods for the detection of the presence of sperm DNA fragmentation in a semen sample. The methods include embedding of sperm cells of the semen sample in a gel, denaturing DNA of the sperm cells, and lysing the nuclear proteins of the sperm cells. The present method includes an ionic surfactant sodium dodycyl sulfate (SDS) and a chaotropic agent urea in the lysis solution for releasing DNA from protamine of chromosome, which significantly reduces the time required for lysis. A kit for detecting sperm DNA fragmentation in a semen sample is also disclosed.

Abstract: A database management engine provides a user interface that allows users to access and modify employee information in a database. The database includes entries for employees, and each database entry includes identifying information about the associated employee. A user can request to modify data within database entries, for instance in order to update information associated with an employee. Responsive to the request, the database management engine identifies liabilities associated with the database modification stemming from associated tax laws. Based on the identified tax liabilities, the engine computes the aggregate tax liability owed by the employer and/or employee. Before modifying a database entry, the engine modifies the user interface to include interface elements detailing the computed aggregate tax liability. The user explicitly can be required to confirm the database modification in view of the aggregate tax liability.

Abstract: An optical probe includes a cylindrical lens adapted to receive and transmit incident light. A light-emitting surface of the cylindrical lens is a curved end surface having a concentric ring-shaped diffractive microstructure. A working position of the optical probe is a position where a diffraction order is 1 when the incident light having a design wavelength between a first wavelength and a second wavelength passes through the diffractive microstructure. When passing through the cylindrical lens, the incident light having the first wavelength produces a diffraction effect with the diffractive microstructure and is converged at a first wavelength working position approximately the same as the working position of the optical probe with the diffraction order of 1. After being refracted by the curved end surface, the incident light having the second wavelength is converged at a second wavelength working position approximately the same as the working position of the optical probe.

Abstract: The present disclosure is directed to a semiconductor package including: a package substrate including a top surface, lateral sides and a bottom surface; a ball grid array including a plurality of solder balls coupled to the bottom surface; a stiffener including a bottom portion affixed to the bottom surface of the package substrate and a lateral portion extending from the bottom portion and affixed to the lateral sides of the package substrate, the bottom portion of the stiffener including a plurality of openings for the plurality of solder balls, wherein the top surface of the package substrate is substantially flush with a top surface of the lateral portion; and an electronic component coupled to the top surface of the package substrate.

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

Abstract: The present invention is related to a laminated thin heat dissipation device mainly comprising an upper plate, at least one first layer plate, at least one second layer plate, a lower plate and a working fluid, the first, second layer plates having at least one first, second hollow slots respectively, wherein the upper plate, the first layer plate, the second layer plate and the lower plate are laminated to form a hollow body, the first hollow slot and the second hollow slot are communicated with each other and form an enclosed chamber, the enclosed chamber includes at least one first fluid channel and at least one second fluid channel, the enclosed chamber of the hollow body is filled with the working fluid, the first fluid channel serves as a vapor flow path, and the second fluid channel serves as a condensed fluid flow path.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: Disclosed herein is a method for the detection of the presence of sperm DNA fragmentation in a semen sample. The method comprises a step of embedding the semen sample containing sperm cells in a gel comprising acrylamide, acrylic acid, methacrylic acid, N-isopropylacrylamide (NIPAM), alginate, or polyethylene glycol (PEG), to obtain a sperm cells-embedded gel. A kit for detecting sperm DNA fragmentation in a semen sample is also disclosed.

Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

Abstract: An interconnect structure is provided. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a capping layer having a first portion, a second portion opposing the first portion, and a third portion connecting the first portion and the second portion, wherein the third portion is in contact with the dielectric layer. The structure also includes a support layer in contact with the first and second portions of the capping layer, a first conductive layer disposed over the first conductive feature, a second conductive layer disposed over the dielectric layer, and a two-dimensional (2D) material layer in contact with a top surface of the first conductive layer, wherein the support layer, the first portion, the second portion, and the third portion define an air gap, and the air gap is disposed between the first conductive layer and the second conductive layer.

Abstract: Some embodiments of the present disclosure relate to an integrated chip, including a semiconductor substrate and a dielectric layer disposed over the semiconductor substrate. A pair of metal lines are disposed over the dielectric layer and laterally spaced apart from one another by a cavity. A barrier layer structure extends along nearest neighboring sidewalls of the pair of metal lines such that the cavity is defined by inner sidewalls of the barrier layer structure and a top surface of the dielectric layer.