Abstract: Techniques are described herein that are capable of automatic mapping of a question or compliance controls associated with a compliance standard to compliance controls associated with another compliance standard. Reference controls having respective first subsets of text-based features are identified. A question having a second subset of the text-based features or custom controls having respective second subsets of the text-based features are identified. Scores for the respective reference controls are determined for the question or each custom control using a supervised natural language processing machine learning model based at least on the first subsets of the text-based features and the second subset(s) of the text-based features. A compliance map is generated by automatically mapping the question or each custom control to a respective subset of the reference controls using the supervised natural language processing machine learning model based at least on the scores.

Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.

Abstract: The present disclosure is relates to a TPU ball structure and a manufacturing method thereof. The TPU ball structure includes a ball bladder layer, a yarn layer and a surface layer. The ball bladder layer is made of TPU material. The yarn layer is made of TPU material, and the yarn layer is disposed to cover the ball bladder layer. The surface layer is made of TPU material, and the surface layer is disposed to cover the yarn layer. The above layers of the TPU ball structure are made of TPU material to satisfy a requirement for environmental protection, and are recyclable. There is no need to use adhesive to adhere the above layers of the TPU ball structure. Therefore, the peeling strength between the layers of the TPU ball structure can be increased so that the whole peeling strength of the TPU ball structure can be increased.

Abstract: A semiconductor structure includes a first active region, a first dummy active region and a second dummy active region, and a first gate structure extending over the first active region in a first direction. The first active region has a first edge extending in the first direction, and a second edge connected to the first edge and extending in a second direction. The first dummy active region has a first edge extending in the first direction and immediately adjacent to the first edge of the first active region. The second dummy active region has a first edge extending in the second direction and immediately adjacent to the second edge of the first active region.

Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.

Abstract: A parallel multi-step bio-reaction system(10) comprising: (a) a substrate arrangement(12) comprising a plurality of bio-reaction substrate holders(18) configured to hold a plurality of bio-reaction substrates(20); (b) a well arrangement(14) comprising a plurality of fluidic wells(22), the fluidic wells(22) corresponding to a plurality of steps of a multi-step bio-reaction; (c) an actuator(16) configured to: (i) move either the substrate arrangement(12) or the well arrangement(14) relative to the other of the substrate arrangement(12) or the well arrangement(14) to change the alignment of the bio-reaction substrates(20) as a group relative to the fluidic wells(22) as a group; and (ii) bring the bio-reaction substrates(20) into and out of contact with fluids in the fluidic wells(22).

Abstract: An internal rotor type nail drive device of electric nail gun, comprising a nailing rod and an internal rotor type rotary actuator that can output a specific rotation angle and can drive the nailing rod to move downward for nailing. Specifically, the rotary actuator comprises a stator and a rotor arranged inside the stator, even groups of electromagnetic mutual action components are configured in pairs between the stator and the rotor, to generate a tangential force to drive the rotor to rotate for a specific rotation angle, and to drive the nailing rod to move for a nailing stroke. The nailing stroke can be determined by a specific rotation angle. Thus, through the above configuration of the rotary actuator, the structure of the electric nail gun can be simplified, and the kinetic energy for nailing can be increased.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: A method for animating fibers in a computer-based animation process, the method comprises: obtaining a fiber cache comprising a plurality of fibers, each of the plurality of fibers comprising a plurality of fiber vertices; obtaining one or more guides, each of the one or more guides comprising a plurality guide vertices; and determining binding information to bind the one or more guides to the fiber cache. Determining the binding information comprises, for each fiber of the fiber cache: associating the fiber with one or more nearby guides; and, for each of the one or more associated nearby guides: associating each fiber vertex with a nearby guide vertex; and determining, for each fiber vertex, a displacement vector between the fiber vertex and the associated nearby guide vertex.

Abstract: In examples, an electronic device comprises a camera to capture an image of a space and a processor coupled to the camera. The processor is to receive the image of the space from the camera; identify a person in the image and a presentation device in the image; identify a head position of the person based on the image; determine whether the person is viewing the presentation device based on the head position; and perform an action relating to the presentation device based on the determination.

Abstract: A semiconductor device is provided. The semiconductor device includes a carrier, an electronic component, an adapter, a first metal wire and a second metal wire. The electronic component is disposed on the carrier. The adapter is disposed on the carrier. The first metal wire connects the electronic component and the adapter. The second metal wire connects the adapter and the carrier.

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.

Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet disposed along an axis and at least one first outlet and a second outlet located in different radial directions, wherein the first outlet and the second outlet are opposite to and separated from each other. The impeller is disposed in the housing along the axis. A heat dissipation system of an electronic device is also provided.

Abstract: An electronic window is provided for adjusting light and includes a first panel, a second panel, and an intermediate layer. The first panel includes a first alignment layer. The second panel includes a second alignment layer. The intermediate layer is disposed between the first panel and the second panel. The angle of orientation of the first alignment layer is between 25 degrees and 65 degrees, and the angle of orientation of the second alignment layer is between 115 degrees and 155 degrees.

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

Abstract: An information handling system includes a battery and a charger. The battery provides a battery voltage to a main power rail of the information handling system and is couplable to the main power rail through a switch. The charger has an output coupled to the main power rail and an input coupled to an external power adapter. The power adapter provides a selectable voltage level to the input. The information handling system selects a particular voltage level that is lower than the battery voltage and directs the switch to decouple the battery from the main power rail when the information handling system is in a soft power-off state.