Patents by Inventor Chin Lin

Chin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144567
    Abstract: A method for animating fibers in a computer-based animation process, the method comprises: obtaining a fiber cache comprising a plurality of fibers, each of the plurality of fibers comprising a plurality of fiber vertices; obtaining one or more guides, each of the one or more guides comprising a plurality guide vertices; and determining binding information to bind the one or more guides to the fiber cache. Determining the binding information comprises, for each fiber of the fiber cache: associating the fiber with one or more nearby guides; and, for each of the one or more associated nearby guides: associating each fiber vertex with a nearby guide vertex; and determining, for each fiber vertex, a displacement vector between the fiber vertex and the associated nearby guide vertex.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Applicant: Digital Domain Virtual Human (US), Inc.
    Inventors: Gene Wei-Chin LIN, Giorgio LAFRATTA, Rafe SACKS, Nathan FOK
  • Publication number: 20240145350
    Abstract: A semiconductor device is provided. The semiconductor device includes a carrier, an electronic component, an adapter, a first metal wire and a second metal wire. The electronic component is disposed on the carrier. The adapter is disposed on the carrier. The first metal wire connects the electronic component and the adapter. The second metal wire connects the adapter and the carrier.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 2, 2024
    Inventors: Pu-Shan HUANG, Chi-Yuan CHEN, Shih-Chin LIN
  • Publication number: 20240141922
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240138098
    Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Yu-Ming Lin
  • Publication number: 20240133949
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Publication number: 20240134136
    Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Formerica Optoelectronics, Inc.
    Inventors: Yun-Cheng HUANG, Yi-Nan SHIH, Chih-Chung LIN, Yun-Chin TSAI
  • Patent number: 11968800
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet disposed along an axis and at least one first outlet and a second outlet located in different radial directions, wherein the first outlet and the second outlet are opposite to and separated from each other. The impeller is disposed in the housing along the axis. A heat dissipation system of an electronic device is also provided.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Kuang-Hua Lin, Sheng-Yan Chen
  • Patent number: 11966121
    Abstract: An electronic window is provided for adjusting light and includes a first panel, a second panel, and an intermediate layer. The first panel includes a first alignment layer. The second panel includes a second alignment layer. The intermediate layer is disposed between the first panel and the second panel. The angle of orientation of the first alignment layer is between 25 degrees and 65 degrees, and the angle of orientation of the second alignment layer is between 115 degrees and 155 degrees.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: April 23, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: En-Hsiang Chen, Chih-Chin Kuo, Mao-Shiang Lin, Hsu-Kuan Hsu
  • Patent number: 11966544
    Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: April 23, 2024
    Assignee: Apple Inc.
    Inventors: Shinya Ono, Suhwan Moon, Dong-Gwang Ha, Jiaxi Hu, Hao-Lin Chiu, Kwang Soon Park, Hassan Edrees, Wen-I Hsieh, Jiun-Jye Chang, Chin-Wei Lin, Kyung Wook Kim
  • Publication number: 20240126358
    Abstract: An information handling system includes a battery and a charger. The battery provides a battery voltage to a main power rail of the information handling system and is couplable to the main power rail through a switch. The charger has an output coupled to the main power rail and an input coupled to an external power adapter. The power adapter provides a selectable voltage level to the input. The information handling system selects a particular voltage level that is lower than the battery voltage and directs the switch to decouple the battery from the main power rail when the information handling system is in a soft power-off state.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Inventors: Hsin-Tien Lin, Jui-Chin Fang, Geroncio Ong Tan, Adolfo S. Montero
  • Patent number: 11961951
    Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 16, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jian-Chin Liang, Shih-Lun Lai, Jo-Hsiang Chen
  • Patent number: 11951477
    Abstract: An example method includes connecting a flow cell to an instrument. The flow cell includes a flow channel including a manifold section having a manifold section swept volume and a detection section having a detection section swept volume. A ratio of the detection section swept volume to manifold section swept volume is at least 10 to 1. A first reagent is pumped through the flow channel. A first chemical reaction is performed between the first reagent and analytes positioned in the detection section. A subsequent reagent is pumped through the flow channel to flush out the remaining reagent. A concentration of at least 99.95 percent of reagent positioned in the detection section is the subsequent reagent, after pumping a total volume of the subsequent reagent through the flow channel that is equal to or less than 2.5 times a total swept volume of the manifold section plus the detection section.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 9, 2024
    Assignee: Illumina, Inc.
    Inventors: Sz-Chin Lin, Jay Taylor, Minsoung Rhee, Jennifer Foley, Wesley Cox-Muranami, Cyril Delattre, Tarun Khurana, Paul Crivelli
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11954271
    Abstract: An active stylus and a method performed by the active stylus are provided. The active stylus includes a touch sensor inside. The touch sensor is arranged corresponding to a preset pen-holding region on an outer surface. The touch sensor is insulated from the pen body, when an external operating subject touches the preset pen-holding region and touches a touch panel, an uplink signal transmitted by the touch panel is coupled to the pen body via the external operating subject, as an uplink interference signal. The signal processing unit is for: generating a compensation signal; obtaining a compensated interference signal generated based on the compensation signal and the uplink interference signal; generating an uplink signal to be processed based on the received uplink signal and the compensated interference signal; and obtaining uplink information based on the uplink signal to be processed.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: April 9, 2024
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Weijen Chang, Chin-Lin Lee
  • Publication number: 20240111192
    Abstract: An optical device includes: a first substrate; a second substrate disposed opposite to the first substrate; a first conductive layer disposed on the first substrate, wherein the first conductive layer includes a first surface and a third side surface connecting to the first surface; a second conductive layer disposed on the second substrate; a sealant disposed between the first conductive layer and the second conductive layer and having a first side and a second side opposite to the first side; a liquid crystal layer disposed between the first conductive layer and the second conductive layer and locating at the first side of the sealant; and a barrier layer disposed between the first conductive layer and the second conductive layer and locating at the second side of the sealant, wherein at least part of the first surface and the third side surface are not covered by the barrier layer.
    Type: Application
    Filed: August 29, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Chin KUO, Mao-Shiang LIN, Hsu-Kuan HSU
  • Publication number: 20240114619
    Abstract: An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit has connection pads. The redistribution layer is electrically connected to the electronic unit and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has first openings disposed corresponding to the connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes first filler particles, and the second insulating layer includes second filler particles. The first filler particles have a first maximum particle size, the second filler particles have a second maximum particle size, and the second maximum particle size is greater than the first maximum particle size.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 4, 2024
    Applicant: InnoLux Corporation
    Inventors: Cheng-Chi WANG, Chin-Ming HUANG, Chien-Feng LI, Chia-Lin YANG
  • Patent number: 11948938
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: 11948842
    Abstract: A device includes a substrate; semiconductor fins extending from the substrate; a liner layer on sidewalls of the semiconductor fins; an etch stop layer over the substrate and extending laterally from a first portion of the liner layer on a first one of the semiconductor fins to a second portion of the line layer on a second one of the semiconductor fins; an isolation structure over the etch stop layer, wherein the etch stop layer and the isolation structure include different materials; a gate dielectric layer over a top surface of the isolation structure; and a dielectric feature extending through the gate dielectric layer and into the isolation structure, wherein the isolation structure and the dielectric feature collectively extend laterally from the first portion of the liner layer to the second portion of the line layer.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Patent number: 11949056
    Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 2, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jo-Hsiang Chen, Shih-Lun Lai, Min-Che Tsai, Jian-Chin Liang
  • Patent number: 11950431
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang