Patents by Inventor Chin-Long Hung

Chin-Long Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for preparing a trench capacitor structure
    Patent number: 7419872
    Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 2, 2008
    Assignee: Promos Technologies, Inc.
    Inventors: Ching Lee, Chin Wen Lee, Chin Long Hung, Zheng Cheng Chen
  • Method for Preparing a Trench Capacitor Structure
    Publication number: 20080096346
    Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
    Type: Application
    Filed: November 21, 2006
    Publication date: April 24, 2008
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: Ching Lee, Chin Wen Lee, Chin Long Hung, Zheng Cheng Chen
  • Volatile memory devices and methods for forming same
    Patent number: 7241659
    Abstract: A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: July 10, 2007
    Assignee: Promos Technologies, Inc.
    Inventors: Chin-Long Hung, Hong-Long Chang, Yueh-Chuan Lee
  • Volatile memory devices and methods for forming same
    Publication number: 20050067648
    Abstract: A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
    Type: Application
    Filed: November 9, 2004
    Publication date: March 31, 2005
    Inventors: Chin-Long Hung, Hong-Long Chang, Yueh-Chuan Lee