Abstract: A semiconductor device is disclosed. The semiconductor device provides a substrate comprising an image sensor region and a circuit region, wherein the circuit region comprises a pad region and a connecting region. A multilayer interconnect structure is formed on the substrate, wherein the multilayer interconnect structure comprises a plurality of dielectric layers, a plurality of lower wirings at the pad region and the connecting region, and a top wiring on at least one of the lower wirings at the connecting region. A passivation layer is formed over the multilayer interconnect structure. A pad structure is formed through the passivation layer and at least one of the dielectric layers on and electrically connected to at least one of the lower wirings at the pad region.

Abstract: An image sensor array includes a substrate having at least three image sensors located therein. The image sensor array also includes a blue filter positioned proximate to the first image sensor; a green filter proximate to the second image sensor; and a red filter proximate to the third image sensor A first microlens is positionally arranged with the blue filter and the first image sensor; a second microlens is positionally arranged with the green filter and the second image sensor; and a third microlens is positionally arranged with the red filter and the third image sensor. The first microlens has a larger effective area than the second microlens, and the second microlens has a larger effective area than the third microlens.

Abstract: CMOS image sensor devices and fabrication methods thereof. A CMOS image sensor device comprises an array of photo-sensing pixels in a first region of a substrate. Each photo-sensing pixel comprises a fully non-salicide transistor and a pinned photodiode. A logic circuit comprises a complementary metal oxide semiconductor (CMOS) transistor in a second region of the substrate, wherein a salicide is formed on the CMOS transistor in the second region but non-salicide is formed on the first region of the substrate.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.