Patents by Inventor Chin-Pen Yeh
Chin-Pen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8981451Abstract: A semiconductor memory device includes a substrate, a well region in the substrate, a patterned first dielectric layer on the substrate extending over the well region, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure includes a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, the first section and the second section intersecting each other in a cross pattern. The patterned second gate structure includes at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure.Type: GrantFiled: June 19, 2013Date of Patent: March 17, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu, Chin-Pen Yeh
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Publication number: 20130277725Abstract: A semiconductor memory device includes a substrate, a well region in the substrate, a patterned first dielectric layer on the substrate extending over the well region, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure includes a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, the first section and the second section intersecting each other in a cross pattern. The patterned second gate structure includes at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure.Type: ApplicationFiled: June 19, 2013Publication date: October 24, 2013Inventors: Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu, Chin-Pen Yeh
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Patent number: 8525243Abstract: A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor.Type: GrantFiled: July 11, 2011Date of Patent: September 3, 2013Assignee: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Patent number: 8487360Abstract: A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern.Type: GrantFiled: September 7, 2010Date of Patent: July 16, 2013Assignee: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu, Chin-Pen Yeh
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Patent number: 8362558Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: GrantFiled: May 4, 2011Date of Patent: January 29, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Patent number: 8319315Abstract: A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other.Type: GrantFiled: July 30, 2010Date of Patent: November 27, 2012Assignee: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Wei-Hsun Hsu, Shuo-Lun Tu, Shih-Chin Lien, Chin-Pen Yeh
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Publication number: 20120292740Abstract: A semiconductor device comprises a semiconductor substrate, a lateral semiconductor diode, a field insulation structure, and a polysilicon resistor. The diode is formed in a surface region of the semiconductor substrate, and includes a cathode electrode and an anode electrode. The field insulation structure is disposed between the cathode and anode electrodes. The polysilicon resistor is formed over the field insulation structure, and between the cathode and anode electrodes. The polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated from the anode electrode.Type: ApplicationFiled: May 19, 2011Publication date: November 22, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh
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Patent number: 8125031Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: GrantFiled: May 4, 2011Date of Patent: February 28, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20120025352Abstract: A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Inventors: Cheng-Chi Lin, Wei-Hsun Hsu, Shuo-Lun Tu, Shih-Chin Lien, Chin-Pen Yeh
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Publication number: 20110266601Abstract: A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Patent number: 8017486Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: GrantFiled: June 22, 2007Date of Patent: September 13, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20110204441Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Patent number: 7999296Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.Type: GrantFiled: April 14, 2008Date of Patent: August 16, 2011Assignee: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20110121373Abstract: A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern.Type: ApplicationFiled: September 7, 2010Publication date: May 26, 2011Inventors: Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu, Chin-Pen Yeh
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Patent number: 7868370Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.Type: GrantFiled: April 14, 2008Date of Patent: January 11, 2011Assignee: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Patent number: 7829408Abstract: The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.Type: GrantFiled: April 24, 2009Date of Patent: November 9, 2010Assignee: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Shin Su, Chien-Wen Chu, Shih-Chin Lien, Chin-Pen Yeh
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Publication number: 20090256184Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.Type: ApplicationFiled: April 14, 2008Publication date: October 15, 2009Applicant: Macronix International Co., Ltd.Inventors: Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20090256183Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.Type: ApplicationFiled: April 14, 2008Publication date: October 15, 2009Applicant: Macronix International Co., LtdInventors: Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20090209075Abstract: The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.Type: ApplicationFiled: April 24, 2009Publication date: August 20, 2009Inventors: Cheng-Chi LIN, Shin Su, Chein-Wen Chu, Shih-Chin Lien, Chin-Pen Yeh
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Patent number: 7525153Abstract: The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.Type: GrantFiled: April 7, 2006Date of Patent: April 28, 2009Assignee: Macronix International Co., LtdInventors: Cheng-Chi Lin, Shin Su, Chien-Wen Chu, Shih-Chin Lien, Chin-Pen Yeh