Patents by Inventor Chin-Pen Yeh

Chin-Pen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080315308
    Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
  • Publication number: 20070108520
    Abstract: The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.
    Type: Application
    Filed: April 7, 2006
    Publication date: May 17, 2007
    Inventors: Cheng-Chi Lin, Shin Su, Chien-Wen Chu, Shih-Chin Lien, Chin-Pen Yeh
  • Publication number: 20050062162
    Abstract: A pad structure of semiconductor device have a special via pattern to divide the IMD layer into separated IMD blocks, so that the wire bonding cracks are reduced or completely inhibited. According to the invention, the pad structure with a single via pattern of the invention does effectively reduce the wire bonding cracks, and the pad structure with two layers of special via patterns of the invention does completely inhibit the wire bonding cracks.
    Type: Application
    Filed: September 22, 2003
    Publication date: March 24, 2005
    Inventors: Yu-Jen Shen, Chin-Pen Yeh