Patents by Inventor Chin-Sheng Yang

Chin-Sheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200201121
    Abstract: An electronic device is provided, including a frame, a working panel and a cover plate. The frame includes a sidewall, and the sidewall includes an outer surface. At least a part of the working panel is disposed in the frame. The cover plate is disposed on the working panel and includes a surface, wherein a surface of the cover plate and an outer surface of the sidewall of the frame are fixed by using an adhesive, and the extension direction of the surface of the cover plate is different than the extension direction of the outer surface of the sidewall of the frame.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 25, 2020
    Inventors: Wen-Cheng HUANG, Ting-Sheng CHEN, Chia-Chun YANG, Chin-Cheng KUO
  • Publication number: 20200117848
    Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
  • Patent number: 10515185
    Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
  • Publication number: 20190272873
    Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
  • Publication number: 20190171789
    Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
  • Patent number: 10311952
    Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
  • Patent number: 10262982
    Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
  • Publication number: 20190088639
    Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.
    Type: Application
    Filed: May 24, 2018
    Publication date: March 21, 2019
    Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
  • Publication number: 20190088638
    Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.
    Type: Application
    Filed: October 17, 2017
    Publication date: March 21, 2019
    Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
  • Patent number: 10153034
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 10090289
    Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
  • Patent number: 10068919
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chin-Sheng Yang
  • Patent number: 9735235
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 15, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20170178716
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Application
    Filed: March 3, 2017
    Publication date: June 22, 2017
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 9653549
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9644835
    Abstract: A twinkling door hanger mainly includes a main decoration, secondary decoration, illumination device and hanging portion. The secondary decoration is configured on the top of the main decoration, being different from the main decoration in material; the illumination device has at least one illumination element configured inside the main decoration; the hanging portion is configured above the main decoration, capable of being hung on a door knob, allowing the present invention to achieve a decoration profiting effect through the configuration of the illumination element.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 9, 2017
    Inventor: Chin-Sheng Yang
  • Patent number: 9627036
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: April 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Publication number: 20170018302
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Application
    Filed: August 11, 2015
    Publication date: January 19, 2017
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 9508734
    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Sheng Yang, Chien-Hung Chen
  • Publication number: 20160329400
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang