Patents by Inventor Chin-Sheng Yang

Chin-Sheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10068919
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chin-Sheng Yang
  • Patent number: 9735235
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 15, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20170178716
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Application
    Filed: March 3, 2017
    Publication date: June 22, 2017
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 9653549
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9644835
    Abstract: A twinkling door hanger mainly includes a main decoration, secondary decoration, illumination device and hanging portion. The secondary decoration is configured on the top of the main decoration, being different from the main decoration in material; the illumination device has at least one illumination element configured inside the main decoration; the hanging portion is configured above the main decoration, capable of being hung on a door knob, allowing the present invention to achieve a decoration profiting effect through the configuration of the illumination element.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 9, 2017
    Inventor: Chin-Sheng Yang
  • Patent number: 9627036
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: April 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Publication number: 20170018302
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Application
    Filed: August 11, 2015
    Publication date: January 19, 2017
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 9508734
    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Sheng Yang, Chien-Hung Chen
  • Publication number: 20160329400
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9490360
    Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 8, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Shing Chen, Ming-Hui Chang, Wei-Ting Wu, Ying-Chou Lai, Horng-Nan Chern, Chorng-Lih Young, Chin-Sheng Yang
  • Publication number: 20160315100
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.
    Type: Application
    Filed: May 18, 2015
    Publication date: October 27, 2016
    Inventor: Chin-Sheng Yang
  • Publication number: 20160276431
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160276434
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9431483
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9395061
    Abstract: A candle-like lighting device includes a candle shell, a stand and a reflector. The candle shell is positioned above the stand at which the reflector is secured and extends inside the candle shell. A control circuit, an illuminator as surrounded by the reflector and a rotating unit are provided within the stand. The candle shell, spinning as driven y the rotating unit, is provided with a void area. Thereby a light from the illuminator transmits through the void area of the reflector for projecting the shape of the void area on a surface of the spinning candle shell in order to achieve the dynamic visual effect.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 19, 2016
    Inventor: Chin-Sheng Yang
  • Publication number: 20160204121
    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.
    Type: Application
    Filed: March 22, 2016
    Publication date: July 14, 2016
    Inventors: Chin-Sheng Yang, Chien-Hung Chen
  • Patent number: 9379182
    Abstract: A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top portion of the fin to form a fin recess and depositing a germanium-based semiconductor into the fin recess as a germanium-based plug. The method comprises etching the shallow trench structure to expose the germanium-based semiconductor side faces. The exposed germanium-based semiconductor undergoes annealing to form high carrier mobility nanowire structures. The nanowire structures can also be formed of different diameters by selective oxidation of some of the deposited germanium-based plugs. Alternately, forming fin structures of different widths results in deposited germanium plugs of different widths to be deposited to form different thicknesses of nanowires.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9328884
    Abstract: An aqua-lamp-based candle-like lighting device includes a stand, an aqua-lamp and a seat. The stand and seat are positioned at a bottom and a top of the aqua-lamp respectively. A control circuit, installed inside the stand, has a heating element by resistance from electricity and an illuminator. The aqua-lamp is in a three-dimensional hollow shape of transparent appearance containing a low boiling temperature fluid in a dense state with a bottom adhered to the heating element. The seat is provided with a receiving port for accommodating a candle. Thereby the low boiling temperature fluid is in a flowing state by contacting a heat source and under lighting by the illuminator when electricity is applied to the stand and the heating element is operating by resistance so as to enhance the decorating effectiveness.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 3, 2016
    Inventor: Chin-Sheng Yang
  • Patent number: 9331184
    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Sheng Yang, Chien-Hung Chen
  • Publication number: 20160086394
    Abstract: A driving behavior analysis method and a system thereof are provided. The system includes a storage unit, a window splitting unit and a processing unit. The storage unit stores a history fuel-consumption sequence, a driving fuel-consumption sequence and a history reference unit. The history fuel-consumption sequence includes history fuel-consumption data and the driving fuel-consumption sequence includes current fuel-consumption data. The window splitting unit separates history fuel-consumption sequence into multiple basic units and separates driving fuel-consumption sequence into multiple consumption units by utilizing a sliding window to move on the two sequences. By ordering the history fuel-consumption data for each basic unit of the history fuel-consumption sequence in a decreasing order, the processing unit generates a decreasing fuel-consumption sequence.
    Type: Application
    Filed: December 12, 2014
    Publication date: March 24, 2016
    Inventors: Chin-Sheng YANG, Yung-Chih CHEN, Chia-Yu HSU, Liang-Chih YU, Pei-Chann CHANG, Kuo-Hua LAI