Patents by Inventor Chin-Szu Lee

Chin-Szu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10872815
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Shao Tzu Lien, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Publication number: 20200312894
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Application
    Filed: June 14, 2020
    Publication date: October 1, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Patent number: 10763116
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Publication number: 20200258777
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Jung-Tang Wu, Shao Tzu Lien, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Patent number: 10658296
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20200149886
    Abstract: A leveling sensor, a load port including a leveling sensor, and a method of leveling a load port using a load port are disclosed. In an embodiment, a sensor includes an accelerometer configured to detect leveling and vibration of a load port and produce a plurality of data; a plurality of indicator lights configured to display a level measurement and a level direction based on the leveling of the load port; a processor configured to process the data produced by the accelerometer; and a wired connection configured to connect the processor to an external device.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Yi-Lin Wang, Jung-Tang Wu, Chin-Szu Lee, Hua-Sheng Chiu
  • Publication number: 20200136027
    Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee
  • Patent number: 10636702
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Shao Tzu Lien, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Publication number: 20200126793
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Publication number: 20200106009
    Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
    Type: Application
    Filed: September 3, 2019
    Publication date: April 2, 2020
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
  • Publication number: 20200105593
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
    Type: Application
    Filed: November 1, 2018
    Publication date: April 2, 2020
    Inventors: Jung-Tang Wu, Shao Tzu Lien, Chi-Hung Liao, Szu-Hua Wu, Liang-Yueh Ou Yang, Chin-Szu Lee
  • Publication number: 20200083168
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20200075299
    Abstract: A method includes placing a wafer on a wafer holder, depositing a film on a front surface of the wafer, and blowing a gas through ports in a redistributor onto a back surface of the wafer at a same time the deposition is performed. The gas is selected from a group consisting of nitrogen (N2), He, Ne, and combinations thereof.
    Type: Application
    Filed: August 1, 2019
    Publication date: March 5, 2020
    Inventors: Jung-Tang Wu, Szu-Hua Wu, Chin-Szu Lee, Yi-Lin Wang
  • Publication number: 20200043739
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 6, 2020
    Inventors: Hong-Ying LIN, Cheng-Yi WU, Alan TU, Chung-Liang CHENG, Li-Hsuan CHU, Ethan HSIAO, Hui-Lin SUNG, Sz-Yuan HUNG, Sheng-Yung LO, C.W. CHIU, Chih-Wei Hsieh, Chin-Szu LEE
  • Patent number: 10533852
    Abstract: A leveling sensor, a load port including a leveling sensor, and a method of leveling a load port using a load port are disclosed. In an embodiment, a sensor includes an accelerometer configured to detect leveling and vibration of a load port and produce a plurality of data; a plurality of indicator lights configured to display a level measurement and a level direction based on the leveling of the load port; a processor configured to process the data produced by the accelerometer; and a wired connection configured to connect the processor to an external device.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Wang, Jung-Tang Wu, Chin-Szu Lee, Hua-Sheng Chiu
  • Publication number: 20200006639
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Application
    Filed: December 5, 2018
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Tang WU, Jui-Hung HO, Chin-Szu LEE, Meng-Yu WU, Szu-Hua WU
  • Patent number: 10522353
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10497729
    Abstract: An image sensor includes a substrate having a first region and a second region. The image sensor further includes a dielectric layer over the substrate. The image sensor further includes a conductive layer over the dielectric layer, wherein in the first region the conductive layer has a grid shape and in the second region a portion of the conductive layer is concave toward the substrate. The image sensor further includes a protective layer, wherein the protective layer is over the conductive layer in the first region, and over a top surface and along sidewalls of the conductive layer in the second region.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Wu, Chun-Chih Lin, Jian-Shin Tsai, Min-Hui Lin, Wen-Shan Chang, Yi-Ming Lin, Chao-Ching Chang, C. H. Chen, Chin-Szu Lee, Y. T. Tsai
  • Publication number: 20190131134
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Hong-Ying LIN, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sean Lo, C.W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Publication number: 20190093220
    Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 28, 2019
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee