Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

Abstract: In a method of manufacturing a semiconductor package, at least one conductive wire is formed on a substrate in a wire bonding process, a ball end of the conductive wire is located above the substrate, a molding material is provided to cover the conductive wire except the ball end, and an EMI shielding layer is formed on the molding material to connect to the ball end. Owing to the ball end is exposed on the molding material, connection area of the EMI shielding layer to the conductive wire is increased to improve connection strength and reliability between the EMI shielding layer and the conductive wire.

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.

Abstract: Method and device for compression bonding are disclosed. During compression bonding a chip to a substrate, an anti-adhesion layer on a stage is provided to contact with a solder resist layer on the substrate. The solder resist layer will not stick to the anti-adhesion layer such that the reduction of bonding precision due to the solder resist layer remains residues on the compression bonding device is preventable.

Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

Abstract: Method and device for compression bonding are disclosed. During compression bonding a chip to a substrate, an anti-adhesion layer on a stage is provided to contact with a solder resist layer on the substrate. The solder resist layer will not stick to the anti-adhesion layer such that the reduction of bonding precision due to the solder resist layer remains residues on the compression bonding device is preventable.

Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

Abstract: A chip on film package includes a chip and a flexible substrate having a film and a circuit layer. The circuit layer is formed on a first surface of the film and electrically connected to the chip. At least one groove is recessed on a second surface of the film. The flexible substrate is bent to form flat portions and at least one curved portion located between the flat portions when it is bonded to external electronic components. The groove is located on the curved portion and provided to protect the curved portion of the flexible substrate from breaking.

Abstract: A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

Abstract: A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

Abstract: A chip on film package includes a chip and a flexible substrate having a film and a circuit layer. The circuit layer is formed on a first surface of the film and electrically connected to the chip. At least one groove is recessed on a second surface of the film. The flexible substrate is bent to form flat portions and at least one curved portion located between the flat portions when it is bonded to external electronic components. The groove is located on the curved portion and provided to protect the curved portion of the flexible substrate from breaking.

Abstract: A semiconductor substrate includes a carrier and leads formed on the carrier, and a space exists between the adjacent leads and reveals a surface of the carrier. A processing method of the semiconductor substrate uses a laser beam passing through the space to etch the carrier such that there are ditches recessed on the carrier. The ditches can increase fluidity of coating fluid, such as underfill, ACF and solder resist. Furthermore, during etching the carrier, the laser beam also can remove residues remained between the leads to improve yield of the semiconductor substrate.

Abstract: A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

Abstract: A layout structure of flexible circuit board includes a flexible substrate and leads formed on a surface of the flexible substrate. Each of the leads has a bump connection end and a curved part. The bump connection end of each of the leads is located on a chip disposition area of the surface and electrically connected to a chip. The curved part has a first connection point and a second connection point, and the length of the curved part is longer than a straight-line distance between the first and second connection points.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A heat dissipation package structure includes a substrate, a chip disposed on the substrate and a heat dissipation sheet. The heat dissipation sheet comprises a covering portion disposed on a back surface of the chip, a first lateral covering portion disposed on a first lateral surface of the chip and a first conducting portion disposed on the substrate. The back surface comprises a first width, the covering portion comprises a second width, the chip comprises a thickness, and there is an interval between the chip and the substrate. The second width is not larger than summation of the first width, double the interval and double the thickness for making the chip disposed between the heat dissipation sheet and the substrate is not within a completely sealed space so as to prevent the heat dissipation sheet from deformation and separation from the chip or the substrate cause of air expansion.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.