Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to one another. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and at least one latch signal to the source drivers based on the lock signal. The source drivers respectively output a plurality of pixel voltages to the display panel according to the latch signal. The training packets and the color data packets are serially transmitted to the source drivers.

Abstract: A source driver including a controller, a plurality of flip-flops, a plurality of shift registers and a plurality of driving channels is provided. The controller extracts control information from an image data stream. Each of the flip-flops respectively receives a corresponding control bit of the control information, and output the corresponding control bit. The shift registers correspond to the flip-flops one by one, and sequentially transmit an enable pulse. Each of the shift registers determines whether to output the enable pulse according to the control bit outputted by the corresponding flip-flop. The driving channels correspond to the shift registers one by one. Each of the driving channels switches an operation state into an enable mode or a disable mode according to the enable pulse outputted by the corresponding shift register.

Abstract: A source driver for driving at least one sub-pixel is disclosed, in which the source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a first gamma resistor string and an operation circuit. The first gamma resistor string includes a plurality of resistors electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage into the gamma voltages. The operation circuit optionally adds increments to the gamma voltages according to a timing control signal, wherein the increments are the same when the gamma voltages are added. The digital to analog converter selecting one of the gamma voltages generated by the operation circuit as a driving voltage based on received digital pixel data.

Abstract: A source driver including a controller, a plurality of flip-flops, a plurality of shift registers and a plurality of driving channels is provided. The controller extracts control information from an image data stream. Each of the flip-flops respectively receives a corresponding control bit of the control information, and output the corresponding control bit. The shift registers correspond to the flip-flops one by one, and sequentially transmit an enable pulse. Each of the shift registers determines whether to output the enable pulse according to the control bit outputted by the corresponding flip-flop. The driving channels correspond to the shift registers one by one. Each of the driving channels switches an operation state into an enable mode or a disable mode according to the enable pulse outputted by the corresponding shift register.

Abstract: A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module.

Abstract: A source driver for driving at least one sub-pixel is disclosed, in which the source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a first gamma resistor string and an operation circuit. The first gamma resistor string includes a plurality of resistors electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage into the gamma voltages. The operation circuit optionally adds increments to the gamma voltages according to a timing control signal, wherein the increments are the same when the gamma voltages are added. The digital to analog converter selecting one of the gamma voltages generated by the operation circuit as a driving voltage based on received digital pixel data.

Abstract: A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit.

Abstract: A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to one another. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and at least one latch signal to the source drivers based on the lock signal. The source drivers respectively output a plurality of pixel voltages to the display panel according to the latch signal. The training packets and the color data packets are serially transmitted to the source drivers.

Abstract: A circuit for resetting a display having at least one driver outputting a driving voltage through an output channel to a corresponding data line of a panel comprises a first switch and a second switch. The first switch is actuated by a control pulse to transfer a reset voltage to the data line of the panel. The second switch is actuated by the control pulse to electrically isolate the output channel of the driver from the data line of the panel, wherein the control pulse is asserted during transient periods resulting from power-on and power-off of the display.

Abstract: An output buffering circuit of a driver device for a display includes a first amplifier circuit having a first input stage, coupled between an upper power supply and a lower power supply, and a first output stage, coupled between the upper power supply and a first intermediate power supply that is greater than the lower power supply, and a second amplifier circuit having a second input stage coupled between the upper power supply and the lower power supply, and a second output stage coupled between a second intermediate power supply that is lower than the upper power supply and the lower power supply.

Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A source driver includes at least a channel, and the channel includes an N-type digital-to-analog converter (NDAC) and an operational amplifier. The NDAC is utilized for receiving input data and selecting one of a plurality of gamma voltages to generate output data according to the input data. The operational amplifier is coupled to the NDAC, and is utilized for amplifying at least the output data to generate an amplified output data. In addition, the channel does not include any P-type digital-to-analog converter.

Abstract: A source driver includes at least a channel, and the channel includes an N-type digital-to-analog converter (NDAC) and an operational amplifier. The NDAC is utilized for receiving input data and selecting one of a plurality of gamma voltages to generate output data according to the input data. The operational amplifier is coupled to the NDAC, and is utilized for amplifying at least the output data to generate an amplified output data. In addition, the channel does not include any P-type digital-to-analog converter.

Abstract: An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V1) and a second voltage (V2) are applied on the upper buffer, and a third voltage (V3) and a fourth voltage (V4) are applied on the lower buffer, wherein V1>V2, V1>V4, V3>V2, and V3>V4. Then, the upper buffer is operated to output data to a plurality of pixels thereby operating the liquid crystals of the pixels over an upper supply range, wherein the upper supply range is from V1 to V2. Thereafter, the lower buffer is operated to output data to the pixels thereby operating the liquid crystals of the pixels over a lower supply range, wherein the lower supply range is from V3 to V4.

Abstract: An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage.

Abstract: An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage.

Abstract: A lighting emitting display, a pixel circuit and a driving method thereof. The pixel circuit includes a driving transistor, a capacitor and a LED. The capacitor receives a first supply voltage and is coupled to a gate of the driving transistor. A cathode of the LED receives a second supply voltage. During a pre-charge period, the gate and the drain of the driving transistor are coupled to an anode of the LED, the source of the driving transistor is coupled to a charging voltage. The source of the driving transistor receives a data signal and the drain and gate of the driving transistor are coupled to each other during a programming period. The source of the driving transistor is coupled to receive the first supply voltage and the drain of the driving transistor is coupled to the anode of the LED during a display period.

Abstract: A source driver and a compensation method for an offset voltage of an output buffer are provided. The source driver includes a storage element, an output buffer, a sampling unit and a first switch. The output buffer has a first input terminal coupled to the storage element and a second input terminal coupled to an output terminal thereof. The output buffer enhances an input signal of the first input terminal and thereby outputs an output signal via the output terminal. The sampling unit respectively transmits a pixel signal and the output signal to the first input terminal of the output buffer and the storage element during a first sub-period for storing an offset voltage of the output buffer in the storage element. The first switch transmits the pixel signal to the storage during a second sub-period for compensating the pixel signal with the offset voltage stored in the storage element.