Abstract: A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module.

Abstract: A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit.

Abstract: A data transmission method for transmitting data between a timing controller and a source driver of a display and a display using the same are disclosed. The transmission method includes recognizing a start of a blank period of a frame period; sampling de-skew data on a data bus during the blank period based on a data clock; performing a de-skew function by comparing the sampled de-skew data with a predetermined de-skew code and adjusting the data clock; recognizing a start of a data input period of the frame period; and sampling pixel data on the data bus during the data input period based on the adjusted data clock. The display includes a timing controller, a data bus, and a source driver. The source driver is connected to the timing controller via the data bus for performing the data transmission method.

Abstract: A source driver includes a gamma voltage generator, in which the gamma voltage generator includes a first gamma resistor string and a second gamma resistor string. The first gamma resistor string receives a first gamma reference voltage and generates a plurality of first gamma voltages. The second gamma resistor string receives a second gamma reference voltage and generates a plurality of second gamma voltages, in which the second gamma voltages have different voltage values from the first gamma voltages. The switch circuit selects the first gamma voltages or the second gamma voltages as output gamma voltages according to a timing control signal. The digital to analog converter selects one of the output gamma voltages as a driving voltage corresponding to a received digital pixel data for driving a first pixel region or a second pixel region of the sub-pixel.

Abstract: A source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a gamma resistor string, a second resistor, a plurality of first switches and a second switch. The first resistors are electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage, in which the first resistors have first ends and second ends for providing gamma voltages. The second resistor has a first end electrically connected to the gamma resistor string and a second end receiving a third gamma reference voltage. The first switches are uniformly conducted to the first ends or the second ends of the first resistors according to a timing control signal for passing the gamma voltages.

Abstract: The present invention discloses an apparatus for driving a display in which each pixels of the display receives a driving voltage and a common voltage, and a luminance of each pixel is determined by a difference between the received driving voltage and the common voltage. The apparatus comprises a plurality of source driver chips, each of which receives a pixel value and generates the driving voltage corresponding to the pixel value according to a plurality of Gamma voltages, wherein at least one of the Gamma voltages is generated by one of the source driver chips.

Abstract: An output buffering circuit of a driver device for a display includes a first amplifier circuit having a first input stage, coupled between an upper power supply and a lower power supply, and a first output stage, coupled between the upper power supply and a first intermediate power supply that is greater than the lower power supply, and a second amplifier circuit having a second input stage coupled between the upper power supply and the lower power supply, and a second output stage coupled between a second intermediate power supply that is lower than the upper power supply and the lower power supply.

Abstract: An OLED display and pixel circuit thereof are provided. The pixel circuit includes first and second switches, first and second PMOS transistors, a capacitor and an OLED. The first switch, controlled by a first scan signal, has a first end receiving a data signal and a second end. The second switch, controlled by a second scan signal, has a third end coupled to the second end and a fourth end. The first PMOS transistor has a source coupled to a high voltage, a drain coupled to the fourth end and a gate coupled to the second end. The second PMOS transistor has a gate coupled to the second end and a source coupled to the high voltage. The capacitor is coupled to the gate of the first PMOS transistor and the high voltage. The OLED has a positive end coupled to a drain of the second PMOS transistor.

Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A luminescent display device is disclosed. The luminescent display device is comprised of an array of pixels, a first driving chip and a second driving chip. The array of pixels is comprised of columns and rows of pixels. The first driving chip is connected a first pixel of the array of pixels, and the second driving chip is connected to a second pixel of the array of pixels. The second pixel is adjacent to the first pixel. The first driving chip is not connected to all pixels in a row of the at least one row of pixels.

Abstract: An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V1) and a second voltage (V2) are applied on the upper buffer, and a third voltage (V3) and a fourth voltage (V4) are applied on the lower buffer, wherein V1>V2, V1>V4, V3>V2, and V3>V4. Then, the upper buffer is operated to output data to a plurality of pixels thereby operating the liquid crystals of the pixels over an upper supply range, wherein the upper supply range is from V1 to V2. Thereafter, the lower buffer is operated to output data to the pixels thereby operating the liquid crystals of the pixels over a lower supply range, wherein the lower supply range is from V3 to V4.

Abstract: A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A digital-to-analog converter outputting an output analog voltage according to an N-bit digital signal is provided. The digital-to-analog converter includes a first and a second resistor strings, a first and a second select units. The first resistor string is connected between a first and a second power supply voltages to generate a first group of reference voltages. The first select unit selects two reference voltages out of the first group according to M most significant bits of the N-bit digital signal. The second resistor string is connected between the selected reference voltages to generate a second group of reference voltages between the selected reference voltages. The second select unit selects one reference voltage out of the second group as the output analog voltage according to the N-M least significant bits of the N-bit digital signal.

Abstract: A circuit for resetting a display having at least one driver outputting a driving voltage through an output channel to a corresponding data line of a panel comprises a first switch and a second switch. The first switch is actuated by a control pulse to transfer a reset voltage to the data line of the panel. The second switch is actuated by the control pulse to electrically isolate the output channel of the driver from the data line of the panel, wherein the control pulse is asserted during transient periods resulting from power-on and power-off of the display.

Abstract: An integrated circuit includes a current mirror circuit for providing a current at an output end, a power-down switch coupled to the output end of the current mirror circuit for controlling access of the current generated by the current mirror circuit based on signals received at a control end of the power-down switch, and a compensating unit coupled to a bias end of the current mirror circuit and the power-down switch for stabilizing voltages at the bias end of the current mirror circuit.

Abstract: The present invention discloses an apparatus for driving a display in which each pixels of the display receives a driving voltage and a common voltage, and a luminance of each pixel is determined by a difference between the received driving voltage and the common voltage. The apparatus comprises a plurality of source driver chips, each of which receives a pixel value and generates the driving voltage corresponding to the pixel value according to a plurality of Gamma voltages. The common voltage is generated by at least one of the source driver chips.

Abstract: The present invention discloses an apparatus for driving a display in which each pixels of the display receives a driving voltage and a common voltage, and a luminance of each pixel is determined by a difference between the received driving voltage and the common voltage. The apparatus comprises a plurality of source driver chips, each of which receives a pixel value and generates the driving voltage corresponding to the pixel value according to a plurality of Gamma voltages, wherein at least one of the Gamma voltages is generated by one of the source driver chips.

Abstract: A luminescent display device is disclosed. The luminescent display device is comprised of an array of pixels, a first driving chip and a second driving chip. The array of pixels is comprised of columns and rows of pixels. The first driving chip is connected a first pixel of the array of pixels, and the second driving chip is connected to a second pixel of the array of pixels. The second pixel is adjacent to the first pixel. The first driving chip is not connected to all pixels in a row of the at least one row of pixels.

Abstract: An integrated circuit includes a current mirror circuit for providing a current at an output end, a power-down switch coupled to the output end of the current mirror circuit for controlling access of the current generated by the current mirror circuit based on signals received at a control end of the power-down switch, and a compensating unit coupled to a bias end of the current mirror circuit and the power-down switch for stabilizing voltages at the bias end of the current mirror circuit.