Patents by Inventor Chin-Yang Hsieh
Chin-Yang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230050587Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.Type: ApplicationFiled: November 3, 2022Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chen-Yi Weng, Jing-Yin Jhang, Hui-Lin Wang, Chin-Yang Hsieh
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Publication number: 20230038528Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 11522127Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.Type: GrantFiled: March 18, 2021Date of Patent: December 6, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Yi Weng, Jing-Yin Jhang, Hui-Lin Wang, Chin-Yang Hsieh
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Patent number: 11508904Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.Type: GrantFiled: May 5, 2021Date of Patent: November 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20220352459Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
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Publication number: 20220302374Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
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Patent number: 11430946Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).Type: GrantFiled: October 7, 2020Date of Patent: August 30, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
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Patent number: 11387408Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.Type: GrantFiled: December 23, 2020Date of Patent: July 12, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
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Publication number: 20220085283Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.Type: ApplicationFiled: November 22, 2021Publication date: March 17, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
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Publication number: 20210399209Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
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Publication number: 20210390993Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Patent number: 11139011Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.Type: GrantFiled: August 29, 2019Date of Patent: October 5, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Patent number: 11139428Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.Type: GrantFiled: September 30, 2019Date of Patent: October 5, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
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Publication number: 20210296572Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20210257542Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.Type: ApplicationFiled: May 5, 2021Publication date: August 19, 2021Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20210226119Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
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Patent number: 11063206Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.Type: GrantFiled: June 12, 2019Date of Patent: July 13, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20210202832Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.Type: ApplicationFiled: March 18, 2021Publication date: July 1, 2021Inventors: Chen-Yi Weng, Jing-Yin Jhang, Hui-Lin Wang, Chin-Yang Hsieh
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Patent number: 11018184Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.Type: GrantFiled: August 6, 2019Date of Patent: May 25, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Ying-Cheng Liu, Yi-Hui Lee, Chin-Yang Hsieh, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20210151666Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.Type: ApplicationFiled: January 4, 2021Publication date: May 20, 2021Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang