Patents by Inventor Chin-Yi Huang

Chin-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11107723
    Abstract: A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 31, 2021
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Long Wang, Zijun Sun, Chin-Chun Huang, Hailong Gu, Penghui Lu, Wen Yi Tan
  • Publication number: 20210262161
    Abstract: The present invention relates to an artificial leather and a method for producing the same. The artificial leather includes a substrate, a thermoplastic polyurethane fiber adhesive layer, a thermoplastic polyurethane fiber layer, a paste layer, and a surface layer. The paste layer has a thermosetting paste or a high solid-content paste, and the paste has a specific adhesive temperature. A bonding can be performed at low temperature in the method for producing the same, and the artificial leather made by the method for producing the same has excellent hand feeling and/or smoothness.
    Type: Application
    Filed: November 16, 2020
    Publication date: August 26, 2021
    Inventors: Chih-Yi LIN, Kuo-Kuang CHENG, Chien-Chia HUANG, Chia-Ho LIN, Yen-Lun TSENG, Chin-Wei CHEN, Ching-Lo LIN
  • Publication number: 20210070861
    Abstract: The present disclosure provides pharmaceutical compositions comprising antibodies and antigen-binding fragments thereof that specifically bind to human B7-H4 (and optionally cynomolgus monkey, mouse, and/or rat B7-H4). The present disclosure also prides methods for treating disorders, such as cancer, by administering such pharmaceutical compositions.
    Type: Application
    Filed: August 19, 2020
    Publication date: March 11, 2021
    Inventors: Yong QUAN, Chin-Yi HUANG, Harjeet Singh GANDA
  • Publication number: 20210066492
    Abstract: A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.
    Type: Application
    Filed: July 13, 2020
    Publication date: March 4, 2021
    Inventors: Chin-Yi HUANG, Wade SHIH
  • Patent number: 10680101
    Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Jyun Syue, Chin-Yi Huang, Kuo-Lung Tzeng, Zhuo-Cang Yang
  • Publication number: 20200098647
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Patent number: 10490460
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Publication number: 20190327442
    Abstract: A display apparatus includes a video processor, a graphics processor, a combining circuit, a retrieving circuit and a graphics controller. The video processor process target video information and generates a corresponding video signal. The graphics processor processes graphic data and generates a corresponding graphic signal. When the target video data changes from first video data to second video data, the retrieving circuit retrieves a static picture associated with the first video data and accordingly generates a retrieval result. The graphics controller utilizes the retrieval result as graphic data provided to the graphics processor. The combining circuit combines the graphic signal on the video signal to generate an output video signal.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 24, 2019
    Inventors: Fu-Min LU, Chin-Yi HUANG, Cheng-Che HSU
  • Publication number: 20190035929
    Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Wan-Jyun SYUE, Chin-Yi HUANG, Kuo-Lung TZENG, Zhuo-Cang YANG
  • Patent number: 10068773
    Abstract: An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao, Chin-Yi Huang
  • Patent number: 10050047
    Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chin-Yi Huang, Ya-Chen Kao
  • Publication number: 20180108576
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 19, 2018
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Patent number: 9865610
    Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu, Chang-Ming Wu
  • Patent number: 9837322
    Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu
  • Patent number: 9768293
    Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region is provided. A first semiconductor region is formed over a second semiconductor region and with a first doping type. The second semiconductor region has a second doping type different than the first doping type. A gate electrode is formed laterally adjacent to the first semiconductor region and extending along a side boundary of the first semiconductor region. A first source/drain contact region and a second source/drain contact region are respectively formed on opposite sides of the gate electrode and with the second doping type. The first source/drain contact region is further formed over the first semiconductor region. A method for manufacturing the LDMOS transistor is also provided.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Jyun Syue, Chin-Yi Huang, Kuo-Lung Tzeng, Zhuo-Cang Yang
  • Patent number: 9747159
    Abstract: Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yue-Der Chih, Hung-Chang Yu, Kai-Chun Lin, Chin-Yi Huang, Laun C. Tran
  • Publication number: 20170221909
    Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Harry-Hak-Lay Chuang, Chin-Yi Huang, Ya-Chen Kao
  • Publication number: 20170162590
    Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu, Chang-Ming Wu
  • Patent number: 9627392
    Abstract: The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chin-Yi Huang, Ya-Chen Kao
  • Patent number: 9583591
    Abstract: The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chin-Yi Huang, Shih-Chang Liu, Chang-Ming Wu