Patents by Inventor Chin-Yu Chen
Chin-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130038Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.Type: ApplicationFiled: November 23, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Chin-Hsun WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Hung, Wei-Yu Liao, Chi-Min Chang
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Patent number: 11944659Abstract: The invention provides a method for improving sarcopenia of a subject in need thereof by using Phellinus linteus, in which the method includes administering an effective dose of composition to the subject, and the composition includes Phellinus linteus (NITE BP-03321 and BCRC 930210) as an effective substance. By using the aforementioned composition including an extract of a fermented product of the Phellinus linteus and/or its derivative, diameters of myotubes, amounts of muscles and muscle muscular endurance can be maintained, thereby improving sarcopenia.Type: GrantFiled: October 12, 2021Date of Patent: April 2, 2024Assignee: GRAPE KING BIO LTDInventors: Chin-Chu Chen, I-Chen Li, Tsung-Ju Li, Ting-Yu Lu, Yen-Po Chen
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Patent number: 11935757Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240088030Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.Type: ApplicationFiled: January 23, 2023Publication date: March 14, 2024Inventors: Chin-Liang CHEN, Chi-Yu LU, Ching-Wei TSAI, Chun-Yuan CHEN, Li-Chun TIEN
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Publication number: 20240072078Abstract: An electronic device including a substrate, a gate line, a switch element, and a photodetector is provided. The gate line is disposed on the substrate. The switch element is disposed on the substrate and is electrically connected to the gate line. The photodetector is disposed on the substrate and electrically connected to the switch element. The photodetector includes a first semiconductor. In a cross-sectional view of the electronic device, a sidewall of the first semiconductor and the gate line are spaced from each other by a first distance. The first distance is greater than or equal to 2 micrometers and less than or equal to 6 micrometers.Type: ApplicationFiled: July 10, 2023Publication date: February 29, 2024Applicant: InnoCare Optoelectronics CorporationInventors: Ting-Yu Chen, Chin-Chi Chen
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Publication number: 20240072075Abstract: An electronic device including a substrate, a first electrode layer, a photodiode, an insulating layer, a second electrode layer, and a first transparent conductive layer is provided. The first electrode layer is disposed on the substrate. The photodiode is disposed on the first electrode layer and is electrically connected to the first electrode layer. The insulating layer is disposed on the photodiode. The second electrode layer is disposed on the insulating layer and is electrically connected to the photodiode. The first transparent conductive layer is disposed on the insulating layer and contacts the second electrode layer. A manufacturing method of an electronic device is also provided.Type: ApplicationFiled: July 18, 2023Publication date: February 29, 2024Applicants: InnoCare Optoelectronics Corporation, Innolux CorporationInventors: Chin-Chi Chen, Ting-Yu Chen, Yi-Ju Tseng, Ji-Zhen Lu
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Publication number: 20240071888Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
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SHOE UPPER DESIGN MODEL GENERATING METHOD, SYSTEM AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIA
Publication number: 20240020438Abstract: This invention provides a shoe upper design model generating method, system and non-transitory computer readable storage media, including steps of providing a 2D mapping boundary, providing a 3D upper, performing a flattening algorithm on the 3D upper with respect to the 2D mapping boundary, constructing a 2D upper boundary, creating an upper design drawing on the 2D upper boundary, intersecting the 2D upper boundary and the 2D mapping boundary to form a 2D upper design area and mapping grids in the 2D upper design area onto grids in the 3D upper, thereby obtaining an upper design model containing the mapping relation between the 2D upper design area and the 3D upper. Accordingly, the upper pattern making time and cost can be saved, and the distortion and deformation in the process of 2D-3D conversion can be reduced, thus the completed 2D upper design drawing can be used in production process directly.Type: ApplicationFiled: April 20, 2023Publication date: January 18, 2024Inventors: Wei-Hsiang TSAI, CHIN-YU CHEN, CHUN-HENG LIN, CHIH-PENG CHEN, FONG-YI SYU -
Patent number: 11848071Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: GrantFiled: December 8, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 11768782Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.Type: GrantFiled: August 3, 2022Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Guan Wang, Ali Feiz Zarrin Ghalam, Chin-Yu Chen, Jongin Kim
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Publication number: 20230057550Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.Type: ApplicationFiled: August 19, 2022Publication date: February 23, 2023Inventors: Chih-Chuan CHEN, Wei-Hsiang TSAI, Chin-Yu CHEN, Ching-Cherng SUN, Jann-Long CHERN, Yu-Kai LIN
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Publication number: 20220374370Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.Type: ApplicationFiled: August 3, 2022Publication date: November 24, 2022Inventors: Guan Wang, Ali Feiz Zarrin Ghalam, Chin-Yu Chen, Jongin Kim
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Patent number: 11442877Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.Type: GrantFiled: October 30, 2020Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Guan Wang, Ali Feiz Zarrin Ghalam, Chin-Yu Chen, Jongin Kim
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Publication number: 20220138120Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Inventors: Guan Wang, Ali Feiz Zarrin Ghalam, Chin-Yu Chen, Jongin Kim
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Publication number: 20220101898Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: ApplicationFiled: December 8, 2021Publication date: March 31, 2022Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: 11211104Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: GrantFiled: November 6, 2020Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Publication number: 20210057007Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: ApplicationFiled: November 6, 2020Publication date: February 25, 2021Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Publication number: 20200402554Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.Type: ApplicationFiled: June 20, 2019Publication date: December 24, 2020Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
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Patent number: D1018537Type: GrantFiled: November 7, 2023Date of Patent: March 19, 2024Assignee: HTC CORPORATIONInventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen