Patents by Inventor Chin-Yu Tsai

Chin-Yu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220208727
    Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 30, 2022
    Inventors: Chin-Chia YANG, Fu-Yu TSAI, Da-Jun LIN, Bin-Siang TSAI
  • Patent number: 11348879
    Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Publication number: 20200350405
    Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventors: Chin-yu Tsai, Guruvayurappan Mathur
  • Patent number: 10756187
    Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chin-yu Tsai, Guruvayurappan Mathur
  • Patent number: 10505037
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chin-Yu Tsai, Imran Khan, Xiaoju Wu
  • Publication number: 20180197986
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: CHIN-YU TSAI, IMRAN KHAN, XIAOJU WU
  • Patent number: 9947783
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chin-Yu Tsai, Imran Khan, Xiaoju Wu
  • Publication number: 20170309744
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+source and a second pwell is on an opposite side of the nwell finger including a p+drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 26, 2017
    Inventors: CHIN-YU TSAI, IMRAN KHAN, XIAOJU WU
  • Publication number: 20170172717
    Abstract: A dental carrier comprises a thermoplastic carrier. The thermoplastic carrier has a pattern structure. After heating the thermoplastic carrier, the thermoplastic carrier is provided with a user to be impressed by teeth or alveolar ridge for forming teeth or alveolar ridge model of the user. Compared to the prior art, the dental carrier of the present invention can provide the dental medicament contained in the pattern structure to be precisely applied and hold onto the treatment area and the medicament can be evenly coated on the teeth, root, or periodontal tissue for the treatment of teeth. When the dental carrier is not used to carry medicament, the pattern structure can improve the mechanical strength and fitness of the dental carrier to be used as a biteplate, orthodontic retainer, periodontal dressing for treatment or protection or mouth guard in sports.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 22, 2017
    Inventors: WIN-PING DENG, HENG-YU LIU, HSIN-HUA CHOU, CHIN-YU TSAI, CHIUNG-FANG HUANG, CHUN-HSIANG WEN, PING-CHEN CHEN, CHING-SUNG CHEN, CHENG-HUSAN LIN, KAI-HAN LIAO
  • Patent number: 9608109
    Abstract: An n-channel DEMOS device a pwell finger defining a length and a width direction formed within a doped surface layer. A first nwell is on one side of the pwell finger including a source and a second nwell on an opposite side of the pwell finger includes a drain. A gate stack is over a channel region the pwell finger between the source and drain. A field dielectric layer is on the surface layer defining a first active area including a first active area boundary along the width direction (WD boundary) that has the channel region therein. A first p-type layer is outside the first active area at least a first minimum distance from the WD boundary and a second p-type layer is doped less and is closer to the WD boundary than the first minimum distance.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: March 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chin-Yu Tsai, Imran Khan, Shaoping Tang
  • Patent number: 6806541
    Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: October 19, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Lily X. Springer, Binghua Hu, Chin-Yu Tsai, Jozef C. Mitros
  • Publication number: 20040169253
    Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.
    Type: Application
    Filed: March 1, 2004
    Publication date: September 2, 2004
    Inventors: Lily X. Springer, Binghua Hu, Chin-Yu Tsai, Jozef C. Mitros
  • Patent number: 6784493
    Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai
  • Patent number: 6770935
    Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: August 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, Dale Skelton
  • Patent number: 6753575
    Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: June 22, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, Chin-Yu Tsai
  • Patent number: 6753202
    Abstract: A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: June 22, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
  • Patent number: 6730569
    Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Lily X. Springer, Binghua Hu, Chin-Yu Tsai, Jozef C. Mitros
  • Patent number: 6729886
    Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, Chin-Yu Tsai
  • Patent number: 6710427
    Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, David D. Briggs, Dale Skelton
  • Patent number: 6709900
    Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai