Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract: An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract: An improved interconnect structure and method of making such a device The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.

Abstract: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

Abstract: An electrical fuse is disclosed. It is formed by a silicide layer on a polysilicon layer, with a first dielectric section separating the electrical fuse from a semiconductor substrate and a second dielectric section separating the electrical fuse from at least one electrical conductor directly above the fuse. The polysilicon layer is at least 2000 Angstroms in thickness and no more than 0.14 um in width and the second dielectric section contains substantially low-K materials.

Abstract: A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.

Abstract: An automatically adjustable wafer probe card for the testing of integrated circuits fabricated on a wafer. The wafer probe card includes a pitch shift assembly having a shift block that includes a reserve needle block and an adjacent functional needle block. Multiple probe needles are linearly adjustable on the shift block, and a selected number of the probe needles can be shifted from the reserve needle block to the functional needle block depending on the number of contact pads on the integrated circuit to be contacted by the probe needles of the wafer probe card during the testing process. A selected spacing between the probe needles, or pitch, can be achieved by locating the probe needles at the selected spacings from each other along the functional needle block.

Abstract: An automatically adjustable wafer probe card for the testing of integrated circuits fabricated on a wafer. The wafer probe card includes a pitch shift assembly having a shift block that includes a reserve needle block and an adjacent functional needle block. Multiple probe needles are linearly adjustable on the shift block, and a selected number of the probe needles can be shifted from the reserve needle block to the functional needle block depending on the number of contact pads on the integrated circuit to be contacted by the probe needles of the wafer probe card during the testing process. A selected spacing between the probe needles, or pitch, can be achieved by locating the probe needles at the selected spacings from each other along the functional needle block.

Abstract: A new method is provided for forming salicided surfaces to a FET device. Gate electrodes are formed including Ti/TiN salicided contact surface regions thereto. A thin layer of silicon oxide and a thick layer of photoresist are deposited. The layer of photoresist is polished, stopping on a top layer of BN of the gate electrode. The exposed layer of BN is removed. A thick layer of Ti/TiN is next deposited and annealed, forming TiSix after which unreacted Ti/TiN is removed. A high temperature anneal is applied to reduce the sheet resistance of the layer of TiSix. As an alternate approach to the above cited sequence the layer of photoresist can be replaced with a layer of boro-phosphate-silicate-glass (BPSG), the layer of BN can be replaced with a layer of silicon nitride.

Abstract: A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.

Abstract: A different method is provided for forming high aspect ratio damascene structures with an integrated approach of combining electroless plating with physical vapor deposition of copper. A dual damascene structure, having a trench opening and a via opening, is first formed over a metal line on a substrate. The inside walls of the dual structure is lined with a diffusion barrier layer. Then, nitride spacers are formed on the inside walls of both the trench opening and the via opening. The via opening is further lined with a displacement, or, seed, layer. This is followed by forming electroless copper in the via opening, and hence a copper plug. A barrier metal is now formed over both the copper plug and the inside walls of the trench opening. Copper is next deposited over the barrier metal inside the trench, and including over the copper metal plug, using physical vapor deposition (PVD).

Abstract: A process for forming a metal—insulator—metal (MIM), capacitor structure, in which platinum is employed for both the capacitor top plate and storage node structures, while a high dielectric constant layer, such as BaTiO3 is used for the capacitor dielectric layer, has been developed. Prior to formation of the MIM capacitor structure, an underlying, platinum storage node plug structure is formed in a narrow diameter opening, allowing communication between the MIM capacitor structure, and regions of an underlying transfer gate transistor, to be realized. A thin ruthenium shape is used as a seed layer to allow an electroless plating procedure to be employed for attainment of the platinum storage node plug structure.

Abstract: The next generation of DRAM capacitors will require base electrodes having large effective surface areas and, additionally, will need to be manufactured with the expenditure of minimal energy (low thermal budgets). This is achieved in the present invention by use of a material other than silicon for the base electrode so that silicon HSGs (hemispherical grains) can be used as masks. By using disilane, rather than the more conventional silane, the HSGs can be formed at significantly lower temperatures and their size and mean separation can be well controlled. With the HSGs in place, the base electrode is etched so that its surface area is significantly increased. After removal of the HSGs, a suitable dielectric layer may be laid down, including high K materials such as barium strontium titanate, and the capacitor completed with the deposition of a suitable top electrode.

Abstract: A first low-k layer is formed over a structure having an exposed active device. A patterned first nitride layer having an opening therethrough aligned over a portion of the active device is formed. Nitride spacers are formed over the side walls of the opening. A second low-k layer is formed over the patterned first nitride layer, filling the patterned first nitride layer opening. The second low-k layer and the first low-k layer through the opening reduced by the nitride spacers are patterned to expose a portion of the active device to form a preliminary dual damascene. The nitride spacers and the first nitride layer exposed by the preliminary dual damascene opening are removed to form a final upper horizontal interconnect opening having substantially 90° edges. The first and second low-k layers are then reflowed to round the substantially 90° edges of the first and second low-k layer.

Abstract: A process for fabricating a capacitor suitable for forming a bottom electrode layer of the capacitor on a substrate. First, a first dielectric layer is formed on a substrate. Then, a portion of the first dielectric layer is removed to form a contact hole. A conductive plug is formed within the contact hole. A seed layer is formed on the conductive plug. A sacrifice layer is formed on both the seed layer and the first dielectric layer. A predetermined region of the sacrifice layer is removed to form a recess so as to expose the seed layer. Then, a bottom electrode layer is formed by electroplating within the recess. The sacrifice layer is removed afterwards. Finally, a second dielectric layer and a top electrode layer are formed on the bottom electrode layer in sequence. The present invention is characterized in that it does not require a direct etching process on a platinum material to. form the bottom electrode layer.

Abstract: A process for fabricating a fin type, cylindrical shaped, DRAM capacitor structure, with increased surface area, has been developed. The process features forming a non-continuous layer of discrete regions of silicon, on the surface of a capacitor opening, in a composite insulator layer. The discrete regions of silicon are then used as an etch mask to allow an isotropic etching procedure to create horizontal channels in the sides of the portions of the composite insulator layer exposed in the capacitor opening, creating a capacitor opening comprised with horizontal channnels. An amorphous silicon layer is then deposited and patterned to form a fin type, storage node structure, comprised of amorphous silicon on discrete regions of silicon, in the capacitor opening. Formation of a capacitor dielectric layer, and an overlying top electrode structure, complete the formation of a fin type, cylindrical shaped, DRAM capacitor structure.

Abstract: A method of forming dual damascene structure is disclosed. A pad oxide layer, a barrier layer and an organic dielectric layer are formed in sequence on a substrate with the conducting line and the organic dielectric layer is etched with a patterned photoresist as a mask to form trenches therein. Next, an anisotropic thickness oxide layer is formed on the substrate by the plasma enhanced chemical vapor deposition (PECVD). Then, the anisotropic thickness oxide layer, the barrier layer and the pad oxide layer are etched with a patterned photoresist as a mask to form vias therein until the conducting line is exposed. Finally, a metal layer is deposited on the substrate and fills the vias and the trenches to form the dual damascene structure.

Abstract: A dual damascene manufacturing process, which is applicable on a dual damascene structure, is described. The etching stop layer at a bottom of the trench line is removed followed by a thermal treatment to smooth out the surface at the bottom of the trench line and in the via to form a larger and smoother opening at the top part of the via. The via and the trench line are then filled with a barrier layer and a metal layer.